Patton electronic 29XX ユーザーズマニュアル
WAN Circuit Configuration—Modify
260
Access Server Administrators’ Reference Guide
22 • T1/E1 Link
Line Type (dsx1LineType)
This variable indicates the type of DS1 Line implemented on this circuit. The type of circuit affects the num-
ber of bits per second that the circuit can reasonably carry, as well as the interpretation of the usage and error
statistics. The values, in sequence, are:
This variable indicates the type of DS1 Line implemented on this circuit. The type of circuit affects the num-
ber of bits per second that the circuit can reasonably carry, as well as the interpretation of the usage and error
statistics. The values, in sequence, are:
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other(1) —Link is disabled
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dsx1ESF(2)—Extended Superframe DS1
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dsx1D4(3)—AT&T D4 format DS1
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dsx1E1(4)—Based on CCITT/ITU G.704 without CRC
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dsx1E1-CRC(5)—Based on CCITT/ITU G.704 with CRC
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dsx1E1-MF(6)—Based on CCITT/ITU G.704 with TS16 multiframing, without CRC
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dsx1E1-CRC-MF(7)—Based on CCITT/ITU G.704 with TS16 multiframing, with CRC
Line Coding (dsx1LineCoding)
This variable describes the type of Zero Code Suppression used on the link, which in turn affects a number of
its characteristics.
This variable describes the type of Zero Code Suppression used on the link, which in turn affects a number of
its characteristics.
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dsx1JBZS(1)—Jammed Bit Zero Suppression, in which the AT&T specification of at least one pulse every
8 bit periods is literally implemented by forcing a pulse in bit 8 of each channel. Thus, only seven bits per
channel, or 1.344 Mbps, is available for data. This feature is not currently implemented.
8 bit periods is literally implemented by forcing a pulse in bit 8 of each channel. Thus, only seven bits per
channel, or 1.344 Mbps, is available for data. This feature is not currently implemented.
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dsx1B8ZS (2)—Binary 8 Zero Suppression. The use of a specified pattern of normal bits and bipolar viola-
tions which are used to replace a sequence of eight zero bits.
tions which are used to replace a sequence of eight zero bits.
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dsx1HDB3(3)—High Density Bipolar Order 3. It is based on AMI but extends this by inserting violation
codes whenever there is a run of 4 or more 0s.
codes whenever there is a run of 4 or more 0s.
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dsx1ZBTSI(4)—May use dsx1ZBTSI, or Zero Byte Time Slot Interchange. This feature is not currently
implemented.
implemented.
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dsx1AMI(5)—Alternate Mark Inversion. Refers to a mode wherein no zero code suppression is present and
the line encoding does not solve the problem directly. In this application, the higher layer must provide data
which meets or exceeds the pulse density requirements, such as inverting HDLC data.
the line encoding does not solve the problem directly. In this application, the higher layer must provide data
which meets or exceeds the pulse density requirements, such as inverting HDLC data.
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other(6)—This feature is not currently supported.
Receive Equalizer (linkRxEqualizer)
This variable determines the equalization used on the received signal. Long haul signals should have the equal-
ization set for more. Short haul signals require less equalization.
This variable determines the equalization used on the received signal. Long haul signals should have the equal-
ization set for more. Short haul signals require less equalization.
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linkRxEqualizerOff(1)
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linkRxEqualizerOn(2)