Intel 253668-032US ユーザーズマニュアル
Vol. 3 4-49
PAGING
in response to an attempted user-mode access) but no other adverse behavior.
Such an exception will occur at most once for each affected linear address (see
Section 4.10.3.1).
Such an exception will occur at most once for each affected linear address (see
Section 4.10.3.1).
•
If a paging-structure entry is modified to change the XD flag from 1 to 0, failure
to perform an invalidation may result in a “spurious” page-fault exception (e.g.,
in response to an attempted instruction fetch) but no other adverse behavior.
Such an exception will occur at most once for each affected linear address (see
Section 4.10.3.1).
to perform an invalidation may result in a “spurious” page-fault exception (e.g.,
in response to an attempted instruction fetch) but no other adverse behavior.
Such an exception will occur at most once for each affected linear address (see
Section 4.10.3.1).
•
If a paging-structure entry is modified to change the accessed flag from 1 to 0,
failure to perform an invalidation may result in the processor not setting that bit
in response to a subsequent access to a linear address whose translation uses the
entry. Software cannot interpret the bit being clear as an indication that such an
access has not occurred.
failure to perform an invalidation may result in the processor not setting that bit
in response to a subsequent access to a linear address whose translation uses the
entry. Software cannot interpret the bit being clear as an indication that such an
access has not occurred.
•
If software modifies a paging-structure entry that identifies the final physical
address for a linear address (either a PTE or a PDE in which the PS flag is 1) to
change the dirty flag from 1 to 0, failure to perform an invalidation may result in
the processor not setting that bit in response to a subsequent write to a linear
address whose translation uses the entry. Software cannot interpret the bit being
clear as an indication that such a write has not occurred.
address for a linear address (either a PTE or a PDE in which the PS flag is 1) to
change the dirty flag from 1 to 0, failure to perform an invalidation may result in
the processor not setting that bit in response to a subsequent write to a linear
address whose translation uses the entry. Software cannot interpret the bit being
clear as an indication that such a write has not occurred.
•
The read of a paging-structure entry in translating an address being used to fetch
an instruction may appear to execute before an earlier write to that paging-
structure entry if there is no serializing instruction between the write and the
instruction fetch. Note that the invalidating instructions identified in Section
4.10.3.1 are all serializing instructions.
an instruction may appear to execute before an earlier write to that paging-
structure entry if there is no serializing instruction between the write and the
instruction fetch. Note that the invalidating instructions identified in Section
4.10.3.1 are all serializing instructions.
•
Section 4.10.2.3 describes situations in which a single paging-structure entry
may contain information cached in multiple entries in the paging-structure
caches. Because all entries in these caches are invalidated by any execution of
INVLPG, it is not necessary to follow the modification of such a paging-structure
entry by executing INVLPG multiple times solely for the purpose of invalidating
these multiple cached entries. (It may be necessary to do so to invalidate
multiple TLB entries.)
may contain information cached in multiple entries in the paging-structure
caches. Because all entries in these caches are invalidated by any execution of
INVLPG, it is not necessary to follow the modification of such a paging-structure
entry by executing INVLPG multiple times solely for the purpose of invalidating
these multiple cached entries. (It may be necessary to do so to invalidate
multiple TLB entries.)
4.10.4
Propagation of Paging-Structure Changes to Multiple
Processors
As noted in Section 4.10.3, software that modifies a paging-structure entry may
need to invalidate entries in the TLBs and paging-structure caches that were derived
from the modified entry before it was modified. In a system containing more than
one logical processor, software must account for the fact that there may be entries in
the TLBs and paging-structure caches of logical processors other than the one used
to modify the paging-structure entry. The process of propagating the changes to a
paging-structure entry is commonly referred to as “TLB shootdown.”
TLB shootdown can be done using memory-based semaphores and/or interprocessor
interrupts (IPI). The following items describe a simple but inefficient example of a
need to invalidate entries in the TLBs and paging-structure caches that were derived
from the modified entry before it was modified. In a system containing more than
one logical processor, software must account for the fact that there may be entries in
the TLBs and paging-structure caches of logical processors other than the one used
to modify the paging-structure entry. The process of propagating the changes to a
paging-structure entry is commonly referred to as “TLB shootdown.”
TLB shootdown can be done using memory-based semaphores and/or interprocessor
interrupts (IPI). The following items describe a simple but inefficient example of a