Intel 253668-032US ユーザーズマニュアル
6-64 Vol. 3
INTERRUPT AND EXCEPTION HANDLING
Interrupt 19—SIMD Floating-Point Exception (#XM)
Exception Class
Fault.
Description
Indicates the processor has detected an SSE/SSE2/SSE3 SIMD floating-point excep-
tion. The appropriate status flag in the MXCSR register must be set and the particular
exception unmasked for this interrupt to be generated.
There are six classes of numeric exception conditions that can occur while executing
an SSE/ SSE2/SSE3 SIMD floating-point instruction:
tion. The appropriate status flag in the MXCSR register must be set and the particular
exception unmasked for this interrupt to be generated.
There are six classes of numeric exception conditions that can occur while executing
an SSE/ SSE2/SSE3 SIMD floating-point instruction:
•
Invalid operation (#I)
•
Divide-by-zero (#Z)
•
Denormal operand (#D)
•
Numeric overflow (#O)
•
Numeric underflow (#U)
•
Inexact result (Precision) (#P)
The invalid operation, divide-by-zero, and denormal-operand exceptions are pre-
computation exceptions; that is, they are detected before any arithmetic operation
occurs. The numeric underflow, numeric overflow, and inexact result exceptions are
post-computational exceptions.
See "SIMD Floating-Point Exceptions" in Chapter 11 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, for additional information
about the SIMD floating-point exception classes.
When a SIMD floating-point exception occurs, the processor does either of the
following things:
computation exceptions; that is, they are detected before any arithmetic operation
occurs. The numeric underflow, numeric overflow, and inexact result exceptions are
post-computational exceptions.
See "SIMD Floating-Point Exceptions" in Chapter 11 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, for additional information
about the SIMD floating-point exception classes.
When a SIMD floating-point exception occurs, the processor does either of the
following things:
•
It handles the exception automatically by producing the most reasonable result
and allowing program execution to continue undisturbed. This is the response to
masked exceptions.
and allowing program execution to continue undisturbed. This is the response to
masked exceptions.
•
It generates a SIMD floating-point exception, which in turn invokes a software
exception handler. This is the response to unmasked exceptions.
exception handler. This is the response to unmasked exceptions.
Each of the six SIMD floating-point exception conditions has a corresponding flag bit
and mask bit in the MXCSR register. If an exception is masked (the corresponding
mask bit in the MXCSR register is set), the processor takes an appropriate automatic
default action and continues with the computation. If the exception is unmasked (the
corresponding mask bit is clear) and the operating system supports SIMD floating-
point exceptions (the OSXMMEXCPT flag in control register CR4 is set), a software
exception handler is invoked through a SIMD floating-point exception. If the excep-
tion is unmasked and the OSXMMEXCPT bit is clear (indicating that the operating
system does not support unmasked SIMD floating-point exceptions), an invalid
opcode exception (#UD) is signaled instead of a SIMD floating-point exception.
and mask bit in the MXCSR register. If an exception is masked (the corresponding
mask bit in the MXCSR register is set), the processor takes an appropriate automatic
default action and continues with the computation. If the exception is unmasked (the
corresponding mask bit is clear) and the operating system supports SIMD floating-
point exceptions (the OSXMMEXCPT flag in control register CR4 is set), a software
exception handler is invoked through a SIMD floating-point exception. If the excep-
tion is unmasked and the OSXMMEXCPT bit is clear (indicating that the operating
system does not support unmasked SIMD floating-point exceptions), an invalid
opcode exception (#UD) is signaled instead of a SIMD floating-point exception.