Intel 253668-032US ユーザーズマニュアル
8-28 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
8.4.3
MP Initialization Protocol Algorithm for
Intel Xeon Processors
Following a power-up or RESET of an MP system, the processors in the system
execute the MP initialization protocol algorithm to initialize each of the logical proces-
sors on the system bus or coherent link domain. In the course of executing this algo-
rithm, the following boot-up and initialization operations are carried out:
1. Each logical processor is assigned a unique APIC ID, based on system topology.
execute the MP initialization protocol algorithm to initialize each of the logical proces-
sors on the system bus or coherent link domain. In the course of executing this algo-
rithm, the following boot-up and initialization operations are carried out:
1. Each logical processor is assigned a unique APIC ID, based on system topology.
The unique ID is a 32-bit value if the processor supports CPUID leaf 0BH,
otherwise the unique ID is an 8-bit value. (see Section 8.4.5, “Identifying Logical
Processors in an MP System”). This ID is written into the local APIC ID register for
each processor.
otherwise the unique ID is an 8-bit value. (see Section 8.4.5, “Identifying Logical
Processors in an MP System”). This ID is written into the local APIC ID register for
each processor.
2. Each logical processor is assigned a unique arbitration priority based on its
APIC ID.
3. Each logical processor executes its internal BIST simultaneously with the other
logical processors on the system bus.
4. Upon completion of the BIST, the logical processors use a hardware-defined
selection mechanism to select the BSP and the APs from the available logical
processors on the system bus. The BSP selection mechanism differs depending
on the family, model, and stepping IDs of the processors, as follows:
— Family, model, and stepping IDs of F0AH and onwards:
processors on the system bus. The BSP selection mechanism differs depending
on the family, model, and stepping IDs of the processors, as follows:
— Family, model, and stepping IDs of F0AH and onwards:
•
The logical processors begin monitoring the BNR# signal, which is
toggling. When the BNR# pin stops toggling, each processor attempts to
issue a NOP special cycle on the system bus.
issue a NOP special cycle on the system bus.
•
The logical processor with the highest arbitration priority succeeds in
issuing a NOP special cycle and is nominated the BSP. This processor sets
the BSP flag in its IA32_APIC_BASE MSR, then fetches and begins
executing BIOS boot-strap code, beginning at the reset vector (physical
address FFFF FFF0H).
the BSP flag in its IA32_APIC_BASE MSR, then fetches and begins
executing BIOS boot-strap code, beginning at the reset vector (physical
address FFFF FFF0H).
•
The remaining logical processors (that failed in issuing a NOP special
cycle) are designated as APs. They leave their BSP flags in the clear state
and enter a “wait-for-SIPI state.”
and enter a “wait-for-SIPI state.”
— Family, model, and stepping IDs up to F09H:
•
Each processor broadcasts a BIPI to “all including self.” The first processor
that broadcasts a BIPI (and thus receives its own BIPI vector), selects
itself as the BSP and sets the BSP flag in its IA32_APIC_BASE MSR. (See
Appendix C.1, “Overview of the MP Initialization Process For P6 Family
Processors,” for a description of the BIPI, FIPI, and SIPI messages.)
itself as the BSP and sets the BSP flag in its IA32_APIC_BASE MSR. (See
Appendix C.1, “Overview of the MP Initialization Process For P6 Family
Processors,” for a description of the BIPI, FIPI, and SIPI messages.)
•
The remainder of the processors (which were not selected as the BSP) are
designated as APs. They leave their BSP flags in the clear state and enter
a “wait-for-SIPI state.”
a “wait-for-SIPI state.”