Intel 253668-032US ユーザーズマニュアル

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Vol. 3   8-69
MULTIPLE-PROCESSOR MANAGEMENT
JE Get_Lock
PAUSE
;Short delay
JMP Spin_Lock
Get_Lock:
MOV EAX, 1
XCHG EAX, lockvar ;Try to get lock
CMP EAX, 0 
;Test if successful
JNE Spin_Lock
Critical_Section:
<critical section code>
MOV lockvar, 0
...
Continue:
The spin-wait loop above uses a “test, test-and-set” technique for determining the 
availability of the synchronization variable. This technique is recommended when 
writing spin-wait loops.
In IA-32 processor generations earlier than the Pentium 4 processor, the PAUSE 
instruction is treated as a NOP instruction.
8.10.6.2   Potential Usage of MONITOR/MWAIT in C0 Idle Loops
An operating system may implement different handlers for different idle states. A 
typical OS idle loop on an ACPI-compatible OS is shown in Example 8-24
Example 8-24.  A Typical OS Idle Loop
// WorkQueue is a memory location indicating there is a thread 
// ready to run.  A non-zero value for WorkQueue is assumed to
// indicate the presence of work to be scheduled on the processor.
// The idle loop is entered with interrupts disabled.
WHILE (1) {
IF (WorkQueue) THEN {
// Schedule work at WorkQueue.
} ELSE 
{
// No work to do - wait in appropriate C-state handler depending 
// on Idle time accumulated
IF (IdleTime >= IdleTimeThreshhold) THEN {
// Call appropriate C1, C2, C3 state handler, C1 handler 
// shown below
}
}
}