Intel 253668-032US ユーザーズマニュアル
9-8 Vol. 3
PROCESSOR MANAGEMENT AND INITIALIZATION
•
It allows x87 FPU code to run on an IA-32 processor that has neither an
integrated x87 FPU nor is connected to an external math coprocessor, by using a
floating-point emulator.
integrated x87 FPU nor is connected to an external math coprocessor, by using a
floating-point emulator.
•
It allows floating-point code to be executed using a special or nonstandard
floating-point emulator, selected for a particular application, regardless of
whether an x87 FPU or math coprocessor is present.
floating-point emulator, selected for a particular application, regardless of
whether an x87 FPU or math coprocessor is present.
To emulate floating-point instructions, the EM, MP, and NE flag in control register CR0
should be set as shown in Table 9-3.
should be set as shown in Table 9-3.
Regardless of the value of the EM bit, the Intel486 SX processor generates a device-
not-available exception (#NM) upon encountering any floating-point instruction.
not-available exception (#NM) upon encountering any floating-point instruction.
9.3 CACHE
ENABLING
IA-32 processors (beginning with the Intel486 processor) and Intel 64 processors
contain internal instruction and data caches. These caches are enabled by clearing
the CD and NW flags in control register CR0. (They are set during a hardware reset.)
Because all internal cache lines are invalid following reset initialization, it is not
necessary to invalidate the cache before enabling caching. Any external caches may
require initialization and invalidation using a system-specific initialization and invali-
dation code sequence.
Depending on the hardware and operating system or executive requirements, addi-
tional configuration of the processor’s caching facilities will probably be required.
Beginning with the Intel486 processor, page-level caching can be controlled with the
PCD and PWT flags in page-directory and page-table entries. Beginning with the P6
family processors, the memory type range registers (MTRRs) control the caching
characteristics of the regions of physical memory. (For the Intel486 and Pentium
processors, external hardware can be used to control the caching characteristics of
regions of physical memory.) See Chapter 11, “Memory Cache Control,” for detailed
information on configuration of the caching facilities in the Pentium 4, Intel Xeon, and
P6 family processors and system memory.
contain internal instruction and data caches. These caches are enabled by clearing
the CD and NW flags in control register CR0. (They are set during a hardware reset.)
Because all internal cache lines are invalid following reset initialization, it is not
necessary to invalidate the cache before enabling caching. Any external caches may
require initialization and invalidation using a system-specific initialization and invali-
dation code sequence.
Depending on the hardware and operating system or executive requirements, addi-
tional configuration of the processor’s caching facilities will probably be required.
Beginning with the Intel486 processor, page-level caching can be controlled with the
PCD and PWT flags in page-directory and page-table entries. Beginning with the P6
family processors, the memory type range registers (MTRRs) control the caching
characteristics of the regions of physical memory. (For the Intel486 and Pentium
processors, external hardware can be used to control the caching characteristics of
regions of physical memory.) See Chapter 11, “Memory Cache Control,” for detailed
information on configuration of the caching facilities in the Pentium 4, Intel Xeon, and
P6 family processors and system memory.
Table 9-3. Software Emulation Settings of EM, MP, and NE Flags
CR0 Bit
Value
EM
1
MP
0
NE
1