Intel 253668-032US ユーザーズマニュアル
Vol. 3 9-15
PROCESSOR MANAGEMENT AND INITIALIZATION
following instructions must be located in an identity-mapped page (until such
time that a branch to non-identity mapped pages can be effected).
time that a branch to non-identity mapped pages can be effected).
64-bit mode paging tables must be located in the first 4 GBytes of physical-address
space prior to activating IA-32e mode. This is necessary because the MOV CR3
instruction used to initialize the page-directory base must be executed in legacy
mode prior to activating IA-32e mode (setting CR0.PG = 1 to enable paging).
Because MOV CR3 is executed in protected mode, only the lower 32 bits of the
register are written, limiting the table location to the low 4 GBytes of memory. Soft-
ware can relocate the page tables anywhere in physical memory after IA-32e mode
is activated.
The processor performs 64-bit mode consistency checks whenever software
attempts to modify any of the enable bits directly involved in activating IA-32e mode
(IA32_EFER.LME, CR0.PG, and CR4.PAE). It will generate a general protection fault
(#GP) if consistency checks fail. 64-bit mode consistency checks ensure that the
processor does not enter an undefined mode or state with unpredictable behavior.
64-bit mode consistency checks fail in the following circumstances:
space prior to activating IA-32e mode. This is necessary because the MOV CR3
instruction used to initialize the page-directory base must be executed in legacy
mode prior to activating IA-32e mode (setting CR0.PG = 1 to enable paging).
Because MOV CR3 is executed in protected mode, only the lower 32 bits of the
register are written, limiting the table location to the low 4 GBytes of memory. Soft-
ware can relocate the page tables anywhere in physical memory after IA-32e mode
is activated.
The processor performs 64-bit mode consistency checks whenever software
attempts to modify any of the enable bits directly involved in activating IA-32e mode
(IA32_EFER.LME, CR0.PG, and CR4.PAE). It will generate a general protection fault
(#GP) if consistency checks fail. 64-bit mode consistency checks ensure that the
processor does not enter an undefined mode or state with unpredictable behavior.
64-bit mode consistency checks fail in the following circumstances:
•
An attempt is made to enable or disable IA-32e mode while paging is enabled.
•
IA-32e mode is enabled and an attempt is made to enable paging prior to
enabling physical-address extensions (PAE).
enabling physical-address extensions (PAE).
•
IA-32e mode is active and an attempt is made to disable physical-address
extensions (PAE).
extensions (PAE).
•
If the current CS has the L-bit set on an attempt to activate IA-32e mode.
•
If the TR contains a 16-bit TSS.
9.8.5.1
IA-32e Mode System Data Structures
After activating IA-32e mode, the system-descriptor-table registers (GDTR, LDTR,
IDTR, TR) continue to reference legacy protected-mode descriptor tables. Tables
referenced by the descriptors all reside in the lower 4 GBytes of linear-address space.
After activating IA-32e mode, 64-bit operating-systems should use the LGDT, LLDT,
LIDT, and LTR instructions to load the system-descriptor-table registers with refer-
ences to 64-bit descriptor tables.
IDTR, TR) continue to reference legacy protected-mode descriptor tables. Tables
referenced by the descriptors all reside in the lower 4 GBytes of linear-address space.
After activating IA-32e mode, 64-bit operating-systems should use the LGDT, LLDT,
LIDT, and LTR instructions to load the system-descriptor-table registers with refer-
ences to 64-bit descriptor tables.
9.8.5.2
IA-32e Mode Interrupts and Exceptions
Software must not allow exceptions or interrupts to occur between the time IA-32e
mode is activated and the update of the interrupt-descriptor-table register (IDTR)
that establishes references to a 64-bit interrupt-descriptor table (IDT). This is
because the IDT remains in legacy form immediately after IA-32e mode is activated.
If an interrupt or exception occurs prior to updating the IDTR, a legacy 32-bit inter-
rupt gate will be referenced and interpreted as a 64-bit interrupt gate with unpredict-
able results. External interrupts can be disabled by using the CLI instruction.
Non-maskable interrupts (NMI) must be disabled using external hardware.
mode is activated and the update of the interrupt-descriptor-table register (IDTR)
that establishes references to a 64-bit interrupt-descriptor table (IDT). This is
because the IDT remains in legacy form immediately after IA-32e mode is activated.
If an interrupt or exception occurs prior to updating the IDTR, a legacy 32-bit inter-
rupt gate will be referenced and interpreted as a 64-bit interrupt gate with unpredict-
able results. External interrupts can be disabled by using the CLI instruction.
Non-maskable interrupts (NMI) must be disabled using external hardware.