Intel 253668-032US ユーザーズマニュアル
Vol. 3 9-47
PROCESSOR MANAGEMENT AND INITIALIZATION
If processor core supports Intel Hyper-Threading Technology, the guideline described
in Section 9.11.6.3 also applies.
in Section 9.11.6.3 also applies.
9.11.6.5 Update Loader Enhancements
The update loader presented in Section 9.11.6, “Microcode Update Loader,” is a
minimal implementation that can be enhanced to provide additional functionality.
Potential enhancements are described below:
minimal implementation that can be enhanced to provide additional functionality.
Potential enhancements are described below:
•
BIOS can incorporate multiple updates to support multiple steppings of the
Pentium 4, Intel Xeon, and P6 family processors. This feature provides for
operating in a mixed stepping environment on an MP system and enables a user
to upgrade to a later version of the processor. In this case, modify the loader to
check the CPUID and platform ID bits of the processor that it is running on
against the available headers before loading a particular update. The number of
updates is only limited by available BIOS space.
Pentium 4, Intel Xeon, and P6 family processors. This feature provides for
operating in a mixed stepping environment on an MP system and enables a user
to upgrade to a later version of the processor. In this case, modify the loader to
check the CPUID and platform ID bits of the processor that it is running on
against the available headers before loading a particular update. The number of
updates is only limited by available BIOS space.
•
A loader can load the update and test the processor to determine if the update
was loaded correctly. See Section 9.11.7, “Update Signature and Verification.”
was loaded correctly. See Section 9.11.7, “Update Signature and Verification.”
•
A loader can verify the integrity of the update data by performing a checksum on
the double words of the update summing to zero. See Section 9.11.5, “Microcode
Update Checksum.”
the double words of the update summing to zero. See Section 9.11.5, “Microcode
Update Checksum.”
•
A loader can provide power-on messages indicating successful loading of an
update.
update.
9.11.7
Update Signature and Verification
The Pentium 4, Intel Xeon, and P6 family processors provide capabilities to verify the
authenticity of a particular update and to identify the current update revision. This
section describes the model-specific extensions of processors that support this
feature. The update verification method below assumes that the BIOS will only verify
an update that is more recent than the revision currently loaded in the processor.
CPUID returns a value in a model specific register in addition to its usual register
return values. The semantics of CPUID cause it to deposit an update ID value in the
64-bit model-specific register at address 08BH (IA32_BIOS_SIGN_ID). If no update
is present in the processor, the value in the MSR remains unmodified. The BIOS must
pre-load a zero into the MSR before executing CPUID. If a read of the MSR at 8BH still
returns zero after executing CPUID, this indicates that no update is present.
The update ID value returned in the EDX register after RDMSR executes indicates the
revision of the update loaded in the processor. This value, in combination with the
CPUID value returned in the EAX register, uniquely identifies a particular update. The
signature ID can be directly compared with the update revision field in a microcode
update header for verification of a correct load. No consecutive updates released for
a given stepping of a processor may share the same signature. The processor signa-
ture returned by CPUID differentiates updates for different steppings.
authenticity of a particular update and to identify the current update revision. This
section describes the model-specific extensions of processors that support this
feature. The update verification method below assumes that the BIOS will only verify
an update that is more recent than the revision currently loaded in the processor.
CPUID returns a value in a model specific register in addition to its usual register
return values. The semantics of CPUID cause it to deposit an update ID value in the
64-bit model-specific register at address 08BH (IA32_BIOS_SIGN_ID). If no update
is present in the processor, the value in the MSR remains unmodified. The BIOS must
pre-load a zero into the MSR before executing CPUID. If a read of the MSR at 8BH still
returns zero after executing CPUID, this indicates that no update is present.
The update ID value returned in the EDX register after RDMSR executes indicates the
revision of the update loaded in the processor. This value, in combination with the
CPUID value returned in the EAX register, uniquely identifies a particular update. The
signature ID can be directly compared with the update revision field in a microcode
update header for verification of a correct load. No consecutive updates released for
a given stepping of a processor may share the same signature. The processor signa-
ture returned by CPUID differentiates updates for different steppings.