Intel 253668-032US ユーザーズマニュアル
Vol. 3 10-53
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The SELF IPI register is a write-only register. A RDMSR instruction with address of the
SELF IPI register will raise a GP fault.
The handling and prioritization of a self-IPI sent via the SELF IPI register is architec-
turally identical to that for an IPI sent via the ICR from a legacy xAPIC unit. Specifi-
cally the state of the interrupt would be tracked via the Interrupt Request Register
(IRR) and In Service Register (ISR) and Trigger Mode Register (TMR) as if it were
received from the system bus. Also sending the IPI via the Self Interrupt Register
ensures that interrupt is delivered to the processor core. Specifically completion of
the WRMSR instruction to the SELF IPI register implies that the interrupt has been
logged into the IRR. As expected for edge triggered interrupts, depending on the
processor priority and readiness to accept interrupts, it is possible that interrupts
sent via the SELF IPI register or via the ICR with identical vectors can be combined.
SELF IPI register will raise a GP fault.
The handling and prioritization of a self-IPI sent via the SELF IPI register is architec-
turally identical to that for an IPI sent via the ICR from a legacy xAPIC unit. Specifi-
cally the state of the interrupt would be tracked via the Interrupt Request Register
(IRR) and In Service Register (ISR) and Trigger Mode Register (TMR) as if it were
received from the system bus. Also sending the IPI via the Self Interrupt Register
ensures that interrupt is delivered to the processor core. Specifically completion of
the WRMSR instruction to the SELF IPI register implies that the interrupt has been
logged into the IRR. As expected for edge triggered interrupts, depending on the
processor priority and readiness to accept interrupts, it is possible that interrupts
sent via the SELF IPI register or via the ICR with identical vectors can be combined.
10.8
SYSTEM AND APIC BUS ARBITRATION
When several local APICs and the I/O APIC are sending IPI and interrupt messages
on the system bus (or APIC bus), the order in which the messages are sent and
handled is determined through bus arbitration.
For the Pentium 4 and Intel Xeon processors, the local and I/O APICs use the arbitra-
tion mechanism defined for the system bus to determine the order in which IPIs are
handled. This mechanism is non-architectural and cannot be controlled by software.
For the P6 family and Pentium processors, the local and I/O APICs use an APIC-based
arbitration mechanism to determine the order in which IPIs are handled. Here, each
local APIC is given an arbitration priority of from 0 to 15, which the I/O APIC uses
during arbitration to determine which local APIC should be given access to the APIC
bus. The local APIC with the highest arbitration priority always wins bus access. Upon
completion of an arbitration round, the winning local APIC lowers its arbitration
priority to 0 and the losing local APICs each raise theirs by 1.
The current arbitration priority for a local APIC is stored in a 4-bit, software-trans-
parent arbitration ID (Arb ID) register. During reset, this register is initialized to the
APIC ID number (stored in the local APIC ID register). The INIT level-deassert IPI,
which is issued with and ICR command, can be used to resynchronize the arbitration
on the system bus (or APIC bus), the order in which the messages are sent and
handled is determined through bus arbitration.
For the Pentium 4 and Intel Xeon processors, the local and I/O APICs use the arbitra-
tion mechanism defined for the system bus to determine the order in which IPIs are
handled. This mechanism is non-architectural and cannot be controlled by software.
For the P6 family and Pentium processors, the local and I/O APICs use an APIC-based
arbitration mechanism to determine the order in which IPIs are handled. Here, each
local APIC is given an arbitration priority of from 0 to 15, which the I/O APIC uses
during arbitration to determine which local APIC should be given access to the APIC
bus. The local APIC with the highest arbitration priority always wins bus access. Upon
completion of an arbitration round, the winning local APIC lowers its arbitration
priority to 0 and the losing local APICs each raise theirs by 1.
The current arbitration priority for a local APIC is stored in a 4-bit, software-trans-
parent arbitration ID (Arb ID) register. During reset, this register is initialized to the
APIC ID number (stored in the local APIC ID register). The INIT level-deassert IPI,
which is issued with and ICR command, can be used to resynchronize the arbitration
Figure 10-23. SELF IPI register
MSR Address: 083FH
31
8 7
0
Reserved
Vector