Intel 253668-032US ユーザーズマニュアル
Vol. 3 13-5
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND
The SIMD floating-point exception mask bits (bits 7 through 12), the flush-to-zero
flag (bit 15), the denormals-are-zero flag (bit 6), and the rounding control field (bits
13 and 14) in the MXCSR register should be left in their default values of 0. This
permits the application to determine how these features are to be used.
flag (bit 15), the denormals-are-zero flag (bit 6), and the rounding control field (bits
13 and 14) in the MXCSR register should be left in their default values of 0. This
permits the application to determine how these features are to be used.
13.1.5
Providing Non-Numeric Exception Handlers for Exceptions
Generated by the SSE/SSE2/SSE3/SSSE3/SSE4 Instructions
SSE/SSE2/SSE3/SSSE3/SSE4 instructions can generate the same type of memory
access exceptions (such as, page fault, segment not present, and limit violations)
and other non-numeric exceptions as other Intel 64 and IA-32 architecture instruc-
tions generate.
Ordinarily, existing exception handlers can handle these and other non-numeric
exceptions without code modification. However, depending on the mechanisms used
in existing exception handlers, some modifications might need to be made.
The SSE/SSE2/SSE3/SSSE3/SSE4 extensions can generate the non-numeric excep-
tions listed below:
access exceptions (such as, page fault, segment not present, and limit violations)
and other non-numeric exceptions as other Intel 64 and IA-32 architecture instruc-
tions generate.
Ordinarily, existing exception handlers can handle these and other non-numeric
exceptions without code modification. However, depending on the mechanisms used
in existing exception handlers, some modifications might need to be made.
The SSE/SSE2/SSE3/SSSE3/SSE4 extensions can generate the non-numeric excep-
tions listed below:
•
Memory Access Exceptions:
— Invalid opcode (#UD).
— Stack-segment fault (#SS).
— General protection (#GP). Executing most SSE/SSE2/SSE3 instructions with
— Invalid opcode (#UD).
— Stack-segment fault (#SS).
— General protection (#GP). Executing most SSE/SSE2/SSE3 instructions with
an unaligned 128-bit memory reference generates a general-protection
exception. (The MOVUPS and MOVUPD instructions allow unaligned a loads or
stores of 128-bit memory locations, without generating a general-protection
exception.) A 128-bit reference within the stack segment that is not aligned
exception. (The MOVUPS and MOVUPD instructions allow unaligned a loads or
stores of 128-bit memory locations, without generating a general-protection
exception.) A 128-bit reference within the stack segment that is not aligned
Table 13-2. Action Taken for Combinations of OSFXSR, SSSE3, SSE4, EM, and TS
CR4
CPUID
CR0 Flags
OSFXSR
SSSE3
SSE4_1*
SSE4_2**
EM
TS
Action
0
X***
X
X
#UD exception.
1
0
X
X
#UD exception.
1
1
1
X
#UD exception.
1
1
0
1
#NM exception.
NOTES:
* Applies to SSE4_1 instructions except DPPS, DPPD, ROUNDPS, ROUNDPD, ROUNDSS, ROUNDSD.
** Applies to SSE4_2 instructions except CRC32 and POPCNT.
***X — Don’t care.
** Applies to SSE4_2 instructions except CRC32 and POPCNT.
***X — Don’t care.