Intel 253668-032US ユーザーズマニュアル
14-8 Vol. 3
POWER AND THERMAL MANAGEMENT
•
When the OS timer service transfers control, the application can use RDPMC
(with ECX = 4000_0001H) to read IA32_PERF_FIXED_CTR1 (MSR address 30AH)
to record the unhalted core clocktick (UCC) value; followed by RDPMC
(ECX=4000_0002H) to read IA32_PERF_FIXED_CTR2 (MSR address 30BH) to
record the unhalted reference clocktick (URC) value. This pair of values is needed
for each logical processor for each sampling period.
(with ECX = 4000_0001H) to read IA32_PERF_FIXED_CTR1 (MSR address 30AH)
to record the unhalted core clocktick (UCC) value; followed by RDPMC
(ECX=4000_0002H) to read IA32_PERF_FIXED_CTR2 (MSR address 30BH) to
record the unhalted reference clocktick (URC) value. This pair of values is needed
for each logical processor for each sampling period.
•
The application can calculate the Turbo activity ratio based on the difference of
UCC between each sample period, over the difference of URC difference. The
effective frequency of each sample period of the logical processor, i, can be
estimated by:
(UCC
UCC between each sample period, over the difference of URC difference. The
effective frequency of each sample period of the logical processor, i, can be
estimated by:
(UCC
n+1, i
- UCC
n, i
)/(URC
n+1, i
- URC
n, i
)* Base_operating_ratio* 133.33MHz
It is possible that the OS had requested a lower-performance P-state during a
sampling period. Thus the ratio (UCC
sampling period. Thus the ratio (UCC
n+1, i
- UCC
n, i
)/(URC
n+1, i
- URC
n, i
) can reflect
the average of Turbo activity (driving the ratio above unity) and some lower P-state
transitions (causing the ratio to be < 1).
It is also possible that the OS might requested C-state transitions when the demand
is low. The above ratio generally does not account for cycles any logical processor
was idle. On Intel Core i7 processors, an application can make use of the time stamp
counter (IA-32_TSC) running at a constant frequency (i.e. Base_operating_ratio*
133.33MHz) during C-states. Thus software can calculate ratios that can indicate
fractions of sample period spent in the C0 state, using the unhalted reference clock-
ticks and the invariant TSC. Note the estimate of fraction spent in C0 may be affected
by SMM handler if the system software makes use of the “FREEZE_WHILE_SMM_EN“
capability to freeze performance counter values while the SMM handler is servicing
an SMI (see Chapter 20, “Introduction to Virtual-Machine Extensions”).
transitions (causing the ratio to be < 1).
It is also possible that the OS might requested C-state transitions when the demand
is low. The above ratio generally does not account for cycles any logical processor
was idle. On Intel Core i7 processors, an application can make use of the time stamp
counter (IA-32_TSC) running at a constant frequency (i.e. Base_operating_ratio*
133.33MHz) during C-states. Thus software can calculate ratios that can indicate
fractions of sample period spent in the C0 state, using the unhalted reference clock-
ticks and the invariant TSC. Note the estimate of fraction spent in C0 may be affected
by SMM handler if the system software makes use of the “FREEZE_WHILE_SMM_EN“
capability to freeze performance counter values while the SMM handler is servicing
an SMI (see Chapter 20, “Introduction to Virtual-Machine Extensions”).
14.3.3
Intel Turbo Boost Technology
Intel Turbo Boost Technology is supported in Intel Core i7 processors and Intel Xeon
processors based on Intel microarchitecture (Nehalem). It uses the same principle of
leveraging thermal headroom to dynamically increase processor performance for
single-threaded and multi-threaded/multi-tasking environment. The programming
interface described in Section 14.3.2 also applies to Intel Turbo Boost Technology.
processors based on Intel microarchitecture (Nehalem). It uses the same principle of
leveraging thermal headroom to dynamically increase processor performance for
single-threaded and multi-threaded/multi-tasking environment. The programming
interface described in Section 14.3.2 also applies to Intel Turbo Boost Technology.
14.3.4
Performance and Energy Bias Hint support
Intel 64 processors may support additional software hint to guide the hardware
heuristic of power management features to favor increasing dynamic performance or
conserve energy consumption.
Software can detect processor's capability to support performance-energy bias pref-
erence hint by examining bit 3 of ECX in CPUID leaf 6. The processor supports this
capability if CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a
new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).
heuristic of power management features to favor increasing dynamic performance or
conserve energy consumption.
Software can detect processor's capability to support performance-energy bias pref-
erence hint by examining bit 3 of ECX in CPUID leaf 6. The processor supports this
capability if CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a
new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).