Intel 253668-032US ユーザーズマニュアル
16-16 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
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FREEZE_LBRS_ON_PMI flag (bit 11) — When set, the LBR stack is frozen on a
hardware PMI request (e.g. when a counter overflows and is configured to trigger
PMI).
hardware PMI request (e.g. when a counter overflows and is configured to trigger
PMI).
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FREEZE_PERFMON_ON_PMI flag (bit 12) — When set, a PMI request clears
each of the “ENABLE” field of MSR_PERF_GLOBAL_CTRL MSR (see Figure 30-3) to
disable all the counters.
each of the “ENABLE” field of MSR_PERF_GLOBAL_CTRL MSR (see Figure 30-3) to
disable all the counters.
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FREEZE_WHILE_SMM_EN (bit 14) — If this bit is set, upon the delivery of an
SMI, the processor will clear all the enable bits of IA32_PERF_GLOBAL_CTRL,
save a copy of the content of IA32_DEBUGCTL and disable LBR, BTF, TR, and BTS
fields of IA32_DEBUGCTL before transferring control to the SMI handler. Subse-
quently, the enable bits of IA32_PERF_GLOBAL_CTRL will be set to 1, the saved
copy of IA32_DEBUGCTL prior to SMI delivery will be restored, after the SMI
handler issues RSM to complete its service. Note that system software must
check IA32_DEBUGCTL. to determine if the processor supports the
FREEZE_WHILE_SMM_EN control bit. FREEZE_WHILE_SMM_EN is supported if
IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See
Section 30.11 for details of detecting the presence of IA32_PERF_CAPABILITIES
MSR.
SMI, the processor will clear all the enable bits of IA32_PERF_GLOBAL_CTRL,
save a copy of the content of IA32_DEBUGCTL and disable LBR, BTF, TR, and BTS
fields of IA32_DEBUGCTL before transferring control to the SMI handler. Subse-
quently, the enable bits of IA32_PERF_GLOBAL_CTRL will be set to 1, the saved
copy of IA32_DEBUGCTL prior to SMI delivery will be restored, after the SMI
handler issues RSM to complete its service. Note that system software must
check IA32_DEBUGCTL. to determine if the processor supports the
FREEZE_WHILE_SMM_EN control bit. FREEZE_WHILE_SMM_EN is supported if
IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See
Section 30.11 for details of detecting the presence of IA32_PERF_CAPABILITIES
MSR.
16.4.2
Monitoring Branches, Exceptions, and Interrupts
When the LBR flag (bit 0) in the IA32_DEBUGCTL MSR is set, the processor automat-
ically begins recording branch records for taken branches, interrupts, and exceptions
(except for debug exceptions) in the LBR stack MSRs.
When the processor generates a a debug exception (#DB), it automatically clears the
LBR flag before executing the exception handler. This action does not clear previously
stored LBR stack MSRs. The branch record for the last four taken branches, interrupts
and/or exceptions are retained for analysis.
A debugger can use the linear addresses in the LBR stack to re-set breakpoints in the
breakpoint address registers (DR0 through DR3). This allows a backward trace from
the manifestation of a particular bug toward its source.
If the LBR flag is cleared and TR flag in the IA32_DEBUGCTL MSR remains set, the
processor will continue to update LBR stack MSRs. This is because BTM information
must be generated from entries in the LBR stack. A #DB does not automatically clear
the TR flag.
ically begins recording branch records for taken branches, interrupts, and exceptions
(except for debug exceptions) in the LBR stack MSRs.
When the processor generates a a debug exception (#DB), it automatically clears the
LBR flag before executing the exception handler. This action does not clear previously
stored LBR stack MSRs. The branch record for the last four taken branches, interrupts
and/or exceptions are retained for analysis.
A debugger can use the linear addresses in the LBR stack to re-set breakpoints in the
breakpoint address registers (DR0 through DR3). This allows a backward trace from
the manifestation of a particular bug toward its source.
If the LBR flag is cleared and TR flag in the IA32_DEBUGCTL MSR remains set, the
processor will continue to update LBR stack MSRs. This is because BTM information
must be generated from entries in the LBR stack. A #DB does not automatically clear
the TR flag.
16.4.3
Single-Stepping on Branches, Exceptions, and Interrupts
When software sets both the BTF flag (bit 1) in the IA32_DEBUGCTL MSR and the TF
flag in the EFLAGS register, the processor generates a single-step debug exception
the next time it takes a branch, services an interrupt, or generates an exception. This
mechanism allows the debugger to single-step on control transfers caused by
branches, interrupts, and exceptions. This “control-flow single stepping” helps isolate
flag in the EFLAGS register, the processor generates a single-step debug exception
the next time it takes a branch, services an interrupt, or generates an exception. This
mechanism allows the debugger to single-step on control transfers caused by
branches, interrupts, and exceptions. This “control-flow single stepping” helps isolate