Intel 253668-032US ユーザーズマニュアル
19-2 Vol. 3
ARCHITECTURE COMPATIBILITY
•
Pentium D Processors — A family of dual-core Intel 64 processors that
provides two processor cores in a physical package. Each core is based on the
Intel NetBurst microarchitecture.
provides two processor cores in a physical package. Each core is based on the
Intel NetBurst microarchitecture.
•
Pentium Processor Extreme Editions — A family of dual-core Intel 64
processors that provides two processor cores in a physical package. Each core is
based on the Intel NetBurst microarchitecture and supports Intel Hyper-
Threading Technology.
processors that provides two processor cores in a physical package. Each core is
based on the Intel NetBurst microarchitecture and supports Intel Hyper-
Threading Technology.
•
Intel Core 2 Processors — A family of Intel 64 processors that are based on the
Intel Core microarchitecture. Intel Pentium Dual-Core processors are also based
on the Intel Core microarchitecture.
Intel Core microarchitecture. Intel Pentium Dual-Core processors are also based
on the Intel Core microarchitecture.
•
Intel Atom Processors — A family of IA-32 and Intel 64 processors that are
based on the Intel Atom microarchitecture.
based on the Intel Atom microarchitecture.
19.2 RESERVED
BITS
Throughout this manual, certain bits are marked as reserved in many register and
memory layout descriptions. When bits are marked as undefined or reserved, it is
essential for compatibility with future processors that software treat these bits as
having a future, though unknown effect. Software should follow these guidelines in
dealing with reserved bits:
memory layout descriptions. When bits are marked as undefined or reserved, it is
essential for compatibility with future processors that software treat these bits as
having a future, though unknown effect. Software should follow these guidelines in
dealing with reserved bits:
•
Do not depend on the states of any reserved bits when testing the values of
registers or memory locations that contain such bits. Mask out the reserved bits
before testing.
registers or memory locations that contain such bits. Mask out the reserved bits
before testing.
•
Do not depend on the states of any reserved bits when storing them to memory
or to a register.
or to a register.
•
Do not depend on the ability to retain information written into any reserved bits.
•
When loading a register, always load the reserved bits with the values indicated
in the documentation, if any, or reload them with values previously read from the
same register.
in the documentation, if any, or reload them with values previously read from the
same register.
Software written for existing IA-32 processor that handles reserved bits correctly will
port to future IA-32 processors without generating protection exceptions.
port to future IA-32 processors without generating protection exceptions.
19.3
ENABLING NEW FUNCTIONS AND MODES
Most of the new control functions defined for the P6 family and Pentium processors
are enabled by new mode flags in the control registers (primarily register CR4). This
register is undefined for IA-32 processors earlier than the Pentium processor.
Attempting to access this register with an Intel486 or earlier IA-32 processor results
in an invalid-opcode exception (#UD). Consequently, programs that execute
correctly on the Intel486 or earlier IA-32 processor cannot erroneously enable these
functions. Attempting to set a reserved bit in register CR4 to a value other than its
are enabled by new mode flags in the control registers (primarily register CR4). This
register is undefined for IA-32 processors earlier than the Pentium processor.
Attempting to access this register with an Intel486 or earlier IA-32 processor results
in an invalid-opcode exception (#UD). Consequently, programs that execute
correctly on the Intel486 or earlier IA-32 processor cannot erroneously enable these
functions. Attempting to set a reserved bit in register CR4 to a value other than its