Intel 253668-032US ユーザーズマニュアル
Vol. 3 19-19
ARCHITECTURE COMPATIBILITY
arithmetic. The 16-bit IA-32 math coprocessors do report a denormal-operand
exception in this situation. This difference does not affect existing software.
On the 32-bit x87 FPUs, loading a denormal value that is in single- or double-real
format causes the value to be converted to extended-real format. Loading a
denormal value on the 16-bit IA-32 math coprocessors causes the value to be
converted to an unnormal. If the next instruction is FXTRACT or FXAM, the 32-bit x87
FPUs will give a different result than the 16-bit IA-32 math coprocessors. This change
was made for IEEE Standard 754 compatibility.
On the 32-bit x87 FPUs, loading an SNaN that is in single- or double-real format
causes the FPU to generate an invalid-operation exception. The 16-bit IA-32 math
coprocessors do not raise an exception when loading a signaling NaN. The invalid-
operation exception handler for 16-bit math coprocessor software needs to be
updated to handle this condition when porting software to 32-bit FPUs. This change
was made for IEEE Standard 754 compatibility.
exception in this situation. This difference does not affect existing software.
On the 32-bit x87 FPUs, loading a denormal value that is in single- or double-real
format causes the value to be converted to extended-real format. Loading a
denormal value on the 16-bit IA-32 math coprocessors causes the value to be
converted to an unnormal. If the next instruction is FXTRACT or FXAM, the 32-bit x87
FPUs will give a different result than the 16-bit IA-32 math coprocessors. This change
was made for IEEE Standard 754 compatibility.
On the 32-bit x87 FPUs, loading an SNaN that is in single- or double-real format
causes the FPU to generate an invalid-operation exception. The 16-bit IA-32 math
coprocessors do not raise an exception when loading a signaling NaN. The invalid-
operation exception handler for 16-bit math coprocessor software needs to be
updated to handle this condition when porting software to 32-bit FPUs. This change
was made for IEEE Standard 754 compatibility.
19.18.7.12 FXTRACT Instruction
On the 32-bit x87 FPUs, if the operand is 0 for the FXTRACT instruction, the divide-
by-zero exception is reported and –∞ is delivered to register ST(1). If the operand is
by-zero exception is reported and –∞ is delivered to register ST(1). If the operand is
+∞, no exception is reported. If the operand is 0 on the 16-bit IA-32 math coproces-
sors, 0 is delivered to register ST(1) and no exception is reported. If the operand is
+∞, the invalid-operation exception is reported. These differences have no impact on
+∞, the invalid-operation exception is reported. These differences have no impact on
existing software. Software usually bypasses 0 and ∞. This change is due to the IEEE
Standard 754 recommendation to fully support the “logb” function.
19.18.7.13 Load Constant Instructions
On 32-bit x87 FPUs, rounding control is in effect for the load constant instructions.
Rounding control is not in effect for the 16-bit IA-32 math coprocessors. Results for
the FLDPI, FLDLN2, FLDLG2, and FLDL2E instructions are the same as for the 16-bit
IA-32 math coprocessors when rounding control is set to round to nearest or round
to +∞. They are the same for the FLDL2T instruction when rounding control is set to
Rounding control is not in effect for the 16-bit IA-32 math coprocessors. Results for
the FLDPI, FLDLN2, FLDLG2, and FLDL2E instructions are the same as for the 16-bit
IA-32 math coprocessors when rounding control is set to round to nearest or round
to +∞. They are the same for the FLDL2T instruction when rounding control is set to
round to nearest, round to –∞, or round to zero. Results are different from the 16-bit
IA-32 math coprocessors in the least significant bit of the mantissa if rounding
control is set to round to –∞ or round to 0 for the FLDPI, FLDLN2, FLDLG2, and
IA-32 math coprocessors in the least significant bit of the mantissa if rounding
control is set to round to –∞ or round to 0 for the FLDPI, FLDLN2, FLDLG2, and
FLDL2E instructions; they are different for the FLDL2T instruction if round to +∞ is
specified. These changes were implemented for compatibility with IEEE Standard
754 for Floating-Point Arithmetic recommendations.
specified. These changes were implemented for compatibility with IEEE Standard
754 for Floating-Point Arithmetic recommendations.
19.18.7.14 FSETPM Instruction
With the 32-bit x87 FPUs, the FSETPM instruction is treated as NOP (no operation).
This instruction informs the Intel 287 math coprocessor that the processor is in
protected mode. This change has no impact on existing software. The 32-bit x87
This instruction informs the Intel 287 math coprocessor that the processor is in
protected mode. This change has no impact on existing software. The 32-bit x87