Intel 253668-032US ユーザーズマニュアル
19-38 Vol. 3
ARCHITECTURE COMPATIBILITY
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The initial stack pointer is FFFCH (32-bit operand) or FFFEH (16-bit operand) and
will wrap around to 0H as a result of the POP operation.
will wrap around to 0H as a result of the POP operation.
The result of the memory write is implementation-specific. For example, in P6 family
processors, the result of the memory write is SS:0H plus any scaled index and
displacement. In Pentium processors, the result of the memory write may be either a
stack fault (real mode or protected mode with stack segment size of 64 KByte), or
write to SS:10000H plus any scaled index and displacement (protected mode and
stack segment size exceeds 64 KByte).
processors, the result of the memory write is SS:0H plus any scaled index and
displacement. In Pentium processors, the result of the memory write may be either a
stack fault (real mode or protected mode with stack segment size of 64 KByte), or
write to SS:10000H plus any scaled index and displacement (protected mode and
stack segment size exceeds 64 KByte).
19.31.2 Error Code Pushes
The Intel486 processor implements the error code pushed on the stack as a 16-bit
value. When pushed onto a 32-bit stack, the Intel486 processor only pushes 2 bytes
and updates ESP by 4. The P6 family and Pentium processors’ error code is a full 32
bits with the upper 16 bits set to zero. The P6 family and Pentium processors, there-
fore, push 4 bytes and update ESP by 4. Any code that relies on the state of the upper
16 bits may produce inconsistent results.
value. When pushed onto a 32-bit stack, the Intel486 processor only pushes 2 bytes
and updates ESP by 4. The P6 family and Pentium processors’ error code is a full 32
bits with the upper 16 bits set to zero. The P6 family and Pentium processors, there-
fore, push 4 bytes and update ESP by 4. Any code that relies on the state of the upper
16 bits may produce inconsistent results.
19.31.3 Fault Handling Effects on the Stack
During the handling of certain instructions, such as CALL and PUSHA, faults may
occur in different sequences for the different processors. For example, during far
calls, the Intel486 processor pushes the old CS and EIP before a possible branch fault
is resolved. A branch fault is a fault from a branch instruction occurring from a
segment limit or access rights violation. If a branch fault is taken, the Intel486 and
P6 family processors will have corrupted memory below the stack pointer. However,
the ESP register is backed up to make the instruction restartable. The P6 family
processors issue the branch before the pushes. Therefore, if a branch fault does
occur, these processors do not corrupt memory below the stack pointer. This imple-
mentation difference, however, does not constitute a compatibility problem, as only
values at or above the stack pointer are considered to be valid. Other operations that
encounter faults may also corrupt memory below the stack pointer and this behavior
may vary on different implementations.
occur in different sequences for the different processors. For example, during far
calls, the Intel486 processor pushes the old CS and EIP before a possible branch fault
is resolved. A branch fault is a fault from a branch instruction occurring from a
segment limit or access rights violation. If a branch fault is taken, the Intel486 and
P6 family processors will have corrupted memory below the stack pointer. However,
the ESP register is backed up to make the instruction restartable. The P6 family
processors issue the branch before the pushes. Therefore, if a branch fault does
occur, these processors do not corrupt memory below the stack pointer. This imple-
mentation difference, however, does not constitute a compatibility problem, as only
values at or above the stack pointer are considered to be valid. Other operations that
encounter faults may also corrupt memory below the stack pointer and this behavior
may vary on different implementations.
19.31.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate
If a call or interrupt is made from a 32-bit stack environment through a 16-bit gate,
only 16 bits of the old ESP can be pushed onto the stack. On the subsequent
RET/IRET, the 16-bit ESP is popped but the full 32-bit ESP is updated since control is
being resumed in a 32-bit stack environment. The Intel486 processor writes the SS
selector into the upper 16 bits of ESP. The P6 family and Pentium processors write
zeros into the upper 16 bits.
only 16 bits of the old ESP can be pushed onto the stack. On the subsequent
RET/IRET, the 16-bit ESP is popped but the full 32-bit ESP is updated since control is
being resumed in a 32-bit stack environment. The Intel486 processor writes the SS
selector into the upper 16 bits of ESP. The P6 family and Pentium processors write
zeros into the upper 16 bits.