HP (Hewlett-Packard) HP 85660B ユーザーズマニュアル

The purpose of the

Phase Detector is to compare the output of the

PLL2 VCO (after division by the

PLL2 Divider) to the 500

Reference from the

Reference Phase Detector. The phase difference is converted to an error voltage used to

correct the PLL2 VCO frequency.

The phase-frequency detector responds to the phase difference between the 500

reference

input and the divided input from the

Divider. Assuming both flip-flops

and

have been cleared,

is on and

is off.

supplies about 3

current which

is sunk by current source

resulting in approximately zero current flow through the 50

low-pass filter to U3. On

PLL2 Phase Detector, HP part number 85660-60276,

transistor

is added as an active

to reduce glitches that could cause momentary

false unlocks.

A pulse from the PLL2 Divider on Pl-19 clocks the Q output of

high, turning

off. A

subsequent reference pulse on Pl-20 clocks the Q output of

high, which will immediately

reset both flip- flops through

Thus the effect of a pulse at Pl-19 leading one at Pl-20 is

to momentarily reduce the output current. Therefore, if the divided output leads the reference

in phase, the current decreases. Similarly, if the reference phase leads, the current increases

because

is connected to the Q output of

If the two inputs have different frequencies, the pulse relationships become complicated, but
the net effect is positive output current if the reference frequency is high.

U3 serves as an amplifier to provide the high currents necessary to rapidly charge the

integrating capacitor C7 in the following stage. VR2 and VR3 serve as clamps, limiting the
output swing to f5.8 V.

When the phase lock loop is in a steady state condition, the voltage at

is zero. If

unlocked, the voltage will be non-zero except for transients passing through zero. When
the voltage

exceeds

V, either

is turned on, discharging Cl5 or Cl4

respectively and tripping comparator

When

voltage settles to less than f0.7 V, Cl4

and Cl5 must recharge before the comparator is reset. This takes 5 ms. The comparator

output is TTL high for an unlock condition and remains there for 5 ms after a lock condition
is established.