Infineon DDR3 2GB Memory Module IMSH2GU13A1F1C-10F ユーザーズマニュアル

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IMSH2GU13A1F1C-10F
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IMSH[1G/2G][U/E]x3A1F1C(T)
DDR3 Unbuffered DIMM
Advance Internet Data Sheet
Rev. 0.65, 2008-12
3
03052008-R2G5-2FN2
1
Overview
This chapter gives an overview of the 240–pin Unbuffered Double-Data-Rate-Three (DDR3) Dual-In-Line memory modules
product family  and describes its main characteristics.
1.1
Features
• 240-pin 8-Byte DDR3 SDRAM unbuffered dual-in-line 
memory modules.
• Module organization: 128M
× 64, 256M × 64, 128M × 72, 
256M
× 72
Chip organization: 128M
× 8
• PC3-12800, PC3-10600, PC3-8500 and PC3-6400  
module speed grades.
• 2-GB, 1-GB modules built with 1-Gbit DDR3 SDRAMs in 
packages PG-TFBGA-78.
• DDR3 SDRAMs with a single  1.5 V (
± 0.075 V) power 
supply.
• Asynchronous Reset.
• Programmable CAS Latency, CAS Write Latency, Additive 
Latency, Burst Length and Burst Type.
• On-Die-Termination (ODT) and Dynamic ODT for 
improved signal integrity.
• Refresh, Self Refresh and Power Down Modes.
• ZQ Calibration for output driver and ODT.
• System Level Timing Calibration Support via Write 
Leveling and Multi Purpose Register (MPR) Read Pattern.
• Serial Presence Detect with EEPROM. 
• Thermal sensor functionality supported.
• UDIMM dimensions: 133.35 mm x 30 mm.
• Based on standard reference raw cards: 'A', 'B', 'D', and 'E'.
• RoHS compliant products1).
TABLE 1
Performance Table for DDR3–1333 and DDR3–1066
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined 
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, 
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit 
www.qimonda.com/green_products
.
2) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also 
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements 
from CL setting as well as requirements from CWL setting. For details, refer to 
QAG Speed Code
–13G
–13H
–10F
–10G
Unit
Note
Module Speed Bin
PC3
–10600G
–10600H
–8500F
–8500G
Device Speed Bin
DDR3
–1333G
–1333H
–1066F
–1066G
CL-
n
RCD
-
n
RP
8-8-8
9-9-9
7-7-7
8-8-8
CL and CWL settings for maximum 
clock frequency
CL = 8
CWL = 7
CL = 9
CWL = 7
CL = 7
CWL = 6
CL = 8
CWL = 6
MHz
Maximum Clock Frequency
and Data Rate
with above CL and CWL settings
667
1333
667
1333
533
1066
533
1066
MHz
Mb/s
Minimum Clock Frequency
and Data Rate
with above CL and CWL settings
533
1066
533
1066
400
800
400
800
MHz
Mb/s