Intel PCI ユーザーズマニュアル
Software Developer’s Manual
225
Register Descriptions
The ADVD3WUC bit (Advertise D3Cold Wakeup Capability Enable control) allows the
AUX_PWR pin to determine whether D3Cold support is advertised. If full 1 Gb/s operation in D3
AUX_PWR pin to determine whether D3Cold support is advertised. If full 1 Gb/s operation in D3
state is desired but the system’s power requirements in this mode would exceed the D3Cold
Wakeup-Enabled specification limit (375 mA at 3.3 V dc), this bit can be used to prevent the
capability from being advertised to the system.
capability from being advertised to the system.
EEPROM settings allow the default PHY behavior to re-negotiate a lower functional link speed in
D3 and D0u states, when PHY operation is still needed for manageability or wakeup capability.
The EN_PHY_PWR_MGMT bit allows this capability to be disabled, in case full 1Gb/s speed is
desired in these states. The PHY is always powered-down in D3 states when unneeded for either
desired in these states. The PHY is always powered-down in D3 states when unneeded for either
manageability or wakeup support.
Table 13-4. Little-Endian Data Ordering
13.4.2
Device Status Register
STATUS (00008h; R)
This register provides software status indication about the Ethernet controller’s settings and modes
of operation.
Note:
TBI Mode is used only by the 82544GC/EI Ethernet controller. Internal SerDes mode is used only
by the 82546GB/EB and 82545GM/EM Ethernet controllers.
by the 82546GB/EB and 82545GM/EM Ethernet controllers.
BEM = 0 (64-bit mode; Little-Endian)
63
0
08
07
06
05
04
03
02
01
10
0f
0e
0d
0c
0b
0a
09