Renesas R5S72627 ユーザーズマニュアル
Section 2 CPU
Page 70 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Classification
Types
Operation
Code
Code
Function
No. of
Instructions
Instructions
Arithmetic
operations
operations
26 ADD Binary
addition
40
ADDC
Binary addition with carry
ADDV
Binary addition with overflow check
CMP/cond
Comparison
CLIPS
Signed saturation value comparison
CLIPU
Unsigned saturation value comparison
DIVS
Signed division (32
32)
DIVU
Unsigned division (32
32)
DIV1
One-step
division
DIV0S
Initialization of signed one-step division
DIV0U
Initialization
of
unsigned one-step division
DMULS
Signed double-precision multiplication
DMULU
Unsigned double-precision multiplication
DT
Decrement and test
EXTS
Sign
extension
EXTU
Zero
extension
MAC
Multiply-and-accumulate,
double-precision
multiply-and-accumulate operation
MUL
Double-precision multiply operation
MULR
Signed multiplication with result storage in Rn
MULS
Signed
multiplication
MULU
Unsigned
multiplication
NEG
Negation
NEGC
Negation with borrow
SUB
Binary
subtraction
SUBC
Binary subtraction with borrow
SUBV
Binary subtraction with underflow