Renesas R5S72627 ユーザーズマニュアル
Section 6 Exception Handling
R01UH0134EJ0400 Rev. 4.00
Page 135 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 6.3 shows the vector numbers and vector table address offsets. Table 6.4 shows how vector
table addresses are calculated.
table addresses are calculated.
Table 6.3
Exception Handling Vector Table
Exception Sources
Vector
Numbers
Numbers
Vector Table Address Offset
Power-on reset
PC
0
H'00000000 to H'00000003
SP 1
H'00000004
to
H'00000007
Manual reset
PC
2
H'00000008 to H'0000000B
SP
3
H'0000000C to H'0000000F
General illegal instruction
4 H'00000010
to
H'00000013
(Reserved by system)
5
H'00000014 to H'00000017
Slot illegal instruction
6
H'00000018 to H'0000001B
(Reserved by system)
7
H'0000001C to H'0000001F
8 H'00000020
to
H'00000023
CPU address error
9
H'00000024 to H'00000027
DMA address error
10
H'00000028 to H'0000002B
Interrupts
NMI
11
H'0000002C to H'0000002F
(Reserved by system)
12
H'00000030 to H'00000033
FPU exception
13
H'00000034 to H'00000037
User debugging interface
14
H'00000038 to H'0000003B
Bank overflow
15
H'0000003C to H'0000003F
Bank underflow
16
H'00000040 to H'00000043
Integer division exception (division by zero)
17
H'00000044 to H'00000047
Integer division exception (overflow) 18 H'00000048
to
H'0000004B
(Reserved by system)
19
:
31
H'0000004C to H'0000004F
:
H'0000007C to H'0000007F
Trap instruction (user vector)
32
:
63
H'00000080 to H'00000083
:
H'000000FC to H'000000FF