Renesas R5S72627 ユーザーズマニュアル
Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00
Page 401 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
If the priority mode bits are modified after a DMA transfer, the channel priority is initialized. If
fixed mode 2 is specified, the channel priority is specified as CH0 > CH8 > CH1 > CH9 > CH2 >
CH10 > CH3 > CH11 > CH4 > CH12 > CH5 > CH13 > CH6 > DH14 > CH7 > CH15. If fixed
mode 1 is specified, the channel priority is specified as CH0 > CH1 > CH2 > CH3 > CH4 > CH5
> CH6 > CH7 > CH8 > CH9 > CH10 > CH11 > CH12 > CH13 > CH14 > CH15.
fixed mode 2 is specified, the channel priority is specified as CH0 > CH8 > CH1 > CH9 > CH2 >
CH10 > CH3 > CH11 > CH4 > CH12 > CH5 > CH13 > CH6 > DH14 > CH7 > CH15. If fixed
mode 1 is specified, the channel priority is specified as CH0 > CH1 > CH2 > CH3 > CH4 > CH5
> CH6 > CH7 > CH8 > CH9 > CH10 > CH11 > CH12 > CH13 > CH14 > CH15.
The internal operation of this module for an address error is as follows:
No address error: Read (source to interior of this module) Write (interior of this module to
destination)
Address error in source address: Nop Nop
Address error in destination address: Read Nop
Address error in destination address: Read Nop