Renesas R5S72627 ユーザーズマニュアル

 

Section 15   Serial Communication Interface with FIFO 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 723 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

2 

 0 

R 

Reserved 

This bit is always read as 0. The write value should 
always be 0. 

1, 0 

CKE[1:0] 

00 

R/W 

Clock Enable 

Select the clock source and enable or disable clock 
output from the SCK pin. Depending on CKE[1:0], the 
SCK pin can be used for serial clock output or serial 
clock input. If serial clock output is set in clock 
synchronous mode, set the C/

A bit in SCSMR to 1, and 

then set CKE[1:0]. Values other than B'00 cannot be 
used for channels that do not have an SCK pin. 

  Asynchronous mode 
00: Internal clock, SCK pin used for input pin (input 

signal is ignored) 

01: Internal clock, SCK pin used for clock output

 

(The output clock frequency is either 16 or 8 times 
the bit rate.) 

10: External clock, SCK pin used for clock input 

(The input clock frequency is either 16 or 8 times 
the bit rate.) 

11: Setting prohibited 

  Clock synchronous mode 
00: Internal clock, SCK pin used for serial clock output 

01: Internal clock, SCK pin used for serial clock output 

10: External clock, SCK pin used for serial clock input 

11: Setting prohibited