Renesas R5S72627 ユーザーズマニュアル
Section 18 Serial Sound Interface
Page 908 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
25
IIRQ
1
R
Idle Mode Interrupt Status Flag
This interrupt status flag indicates whether this module
is in idle state.
is in idle state.
This bit is set regardless of the value of the IIEN bit to
allow polling.
allow polling.
The interrupt can be masked by clearing IIEN, but
cannot be cleared by writing to this bit.
cannot be cleared by writing to this bit.
If IIRQ = 1 and IIEN = 1, an interrupt occurs.
0: This module is not in idle state.
1: This module is in idle state.
24 to 7
Undefined
R
Reserved
The read value is undefined. The write value should
always be 0.
always be 0.
6, 5
TCHNO
[1:0]
[1:0]
00 R
Transmit
Channel
Number
These bits show the current channel number.
These bits indicate which channel is required to be
written to SSITDR. This value will change as the data is
copied to the shift register, regardless of whether the
data is written to SSITDR.
written to SSITDR. This value will change as the data is
copied to the shift register, regardless of whether the
data is written to SSITDR.
4 TSWNO
1
R
Transmit Serial Word Number
This status bit indicates the current word number.
This bit indicates which system word is required to be
written to SSITDR. This value will change as the data is
copied to the shift register, regardless of whether the
data is written to SSITDR.
written to SSITDR. This value will change as the data is
copied to the shift register, regardless of whether the
data is written to SSITDR.
3, 2
RCHNO
[1:0]
[1:0]
00 R
Receive
Channel
Number
These bits show the current channel number.
These bits indicate which channel the data in SSIRDR
currently represents. This value will change as the data
in SSIRDR is updated from the shift register.
currently represents. This value will change as the data
in SSIRDR is updated from the shift register.