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Renesas R5S72625 ユーザーズマニュアル

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Section 20   Controller Area Network 
Page 1038 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
(8)  Unread Message Status Register (UMSR) 
This register is a 32-bit read/conditionally write register and it records the mailboxes whose 
contents have not been accessed by the CPU prior to a new message being received. If the CPU 
has not cleared the corresponding bit in the RXPR or RFPR when a new message for that mailbox 
is received, the corresponding UMSR bit is set to '1'. This bit may be cleared by writing a '1' to the 
corresponding bit location in the UMSR. Writing a '0' has no effect. 
If a mailbox is configured as transmit box, the corresponding UMSR will not be set. 
  UMSR1 
 
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
UMSR1[15:0]
 
Note:  *  Only when writing a '1' to clear. 
 
Bit 15 to 0 — Indicate that an unread received message has been overwritten or overrun condition 
has occurred for Mailboxes 31 to 16.  
Bit[15:0]: UMSR1 
Description 
0 [Clearing 
Condition] 
Writing '1' (initial value) 
1 
Unread received message is overwritten by a new message or overrun 
condition 
[Setting Condition] 
When a new message is received before RXPR or RFPR is cleared 
 
  UMSR0 
 
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
UMSR0[15:0]
 
Note:  *  Only when writing a '1' to clear. 
 
Bit 15 to 0 — Indicate that an unread received message has been overwritten or overrun condition 
has occurred for Mailboxes 15 to 0.