Renesas R5S72623 ユーザーズマニュアル

 
Section 25   NAND Flash Memory Controller 

Page 1294 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

22 4ECCCO 

RRECT 

0 

R/W 

4-Symbol ECC Circuit Correction Execution 

Specifies to execute error correction for a single sector 
when the 4-symbol ECC circuit is used. This module 
suspends sector reading on detection of an ECC error 
and starts error pattern generation by the 4-symbol 
ECC circuit. 

0: Error pattern is not output but only ECC is output. 

1: Reading of sectors is suspended on detection of an 

ECC error. 

21 BUSYON 

0 

R/W 

Busy 

Select 

Specifies whether to release the external bus 
mastership while the FRB pin is busy. The 

FCE pin, 

however, is negated regardless of the busy/ready state 
upon completion of a necessary process. For details, 
see section 25.7.1, External Bus Mastership Release 
Timing. 

0: Holds the bus mastership while the FRB pin is busy. 

1: Releases the bus mastership while the FRB pin is 

busy.  

Note: Some flash memory devices do not allow the 

FCE

pin to be negated during the busy state. 

20 

 1  R 

Reserved 

This bit is always read as 1. The write value should 
always be 1. 

19 

 0  R 

Reserved 

This bit is always read as 0. The write value should 
always be 0. 

18 

SNAND 

0 

R/W 

Large-Capacity NAND Flash Memory Select 

This bit is used to specify 1-Gbit or larger NAND flash 
memory with the page configuration of 2048 + 64 bytes. 

0: When flash memory with the page configuration of 

512 + 16 bytes is used. 

1: When NAND flash memory with the page 

configuration of 2048 + 64 is used.