Renesas R5S72621 ユーザーズマニュアル
Section 22 Renesas SPDIF Interface
R01UH0134EJ0400 Rev. 4.00
Page 1157 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 29
All
0
R
Reserved
28 CKS
0 R/W
Oversampling
clock
select
Selects oversampling clock supply source.
0: AUDIO_X1
1: AUDIO CLK
27
0
R
Reserved
26 PB
0 R/W
Pass
Back
Passes transmitter SPDIF output into SPDIF receiver in
SPDIF module.
SPDIF module.
0: Pass Back disabled
1: Pass Back enabled
25, 24
RASS
All 0
R/W
Receiver Audio Sample Bit Size
These bits Indicate the receiver audio sample bit size (16,
20, or 24 bits), for data alignment purposes.
20, or 24 bits), for data alignment purposes.
00: 16-bit sample
01: 20-bit sample
10: 24-bit sample
11: Reserved
23, 22
TASS
All 0
R/W
Transmitter Audio Sample Bit Size
These bits Indicate the transmitter audio sample bit size
(16, 20, or 24 bits), for data alignment purposes.
(16, 20, or 24 bits), for data alignment purposes.
00: 16-bit sample
01: 20-bit sample
10: 24-bit sample
11: Reserved
21
RDE
0
R/W
Receiver DMA Enable
Enables DMA requests for the receiver.
0: Receiver DMA disabled
1: Receiver DMA enabled
20
TDE
0
R/W
Transmitter DMA Enable
Enables the DMA requests for the transmitter.
0: Transmitter DMA disabled
1: Transmitter DMA enabled