Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート

Datasheet

121

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: 680–687h

Default Value:

0000000000000000h

Access:

RO/P, RO 

Size:

64 bits

This register is used to store the error status information in ECC enabled 

configurations, along with the error syndrome and the rank/bank/row/column address 

information of the address block of main memory of which an error (single bit or multi-

bit error) has occurred. Note that the address fields represent the address of the first 

single or the first multiple bit error occurrence after the error flag bits in the ERRSTS 

register have been cleared by software. A multiple bit error will overwrite a single bit 

error. Once the error flag bits are set as a result of an error, this bit field is locked and 

does not change as a result of a new error until the error flag is cleared by software. 

Same is the case with error syndrome field, but the following priority needs to be 

followed if more than one error occurs on one or more of the 4 QWs. MERR on QW0, 

MERR on QW1, MERR on QW2, MERR on QW3, CERR on QW0, CERR on QW1, CERR on 

QW2, CERR on QW3. 

17:16

RW

00b

DRAM Refresh High Watermark (REFHIGHWM): When the refresh count 
exceeds this level, a refresh request is launched to the scheduler and the 
dref_high flag is set.
00 = 3
01 = 4
10 = 5
11 = 6

15:14

RW

00b

DRAM Refresh Low Watermark (REFLOWWM): When the refresh count 
exceeds this level, a refresh request is launched to the scheduler and the 
dref_low flag is set.
00 = 1
01 = 2
10 = 3
11 = 4

13:0

RW

0011000
0110000

b

Refresh Counter Time Out Value (REFTIMEOUT): Program this field with a 
value that will provide 7.8 us at mclk frequency.
At various memory clock frequencies, this results in the following values:
400 Mhz -> C30 hex (Default Value)
533 Mhz -> 104B hex
666 Mhz -> 1450 hex

63:48

RO/P

0000h

Error Column Address (ERRCOL): Row address of the address block of main 
memory of which an error (single bit or multi-bit error) has occurred. 

47:32

RO/P

0000h

Error Row Address (ERRROW): Row address of the address block of main 
memory of which an error (single bit or multi-bit error) has occurred. 

31:29

RO/P

000b

Error Bank Address (ERRBANK): Rank address of the address block of main 
memory of which an error (single bit or multi-bit error) has occurred.