Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート

製品コード
P4X-UPE3210-316-6M1333
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Datasheet
135
DRAM Controller Registers (D0:F0)
5.2.47
TSTTP—Thermal Sensor Temperature Trip Point
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: CDC–CDFh
Default Value:
00000000h
Access:
RO, RW, RW/L 
Size:
32 bits
This register provides the following:
• Sets the target values for the trip points in thermometer mode. See also TST[Direct 
DAC Connect Test Enable].
• Reports the relative thermal sensor temperature.
All bits in this register are reset to their defaults by MPWROK.
Bit
Access
Default 
Value
Description
31:24
RO
00h
Relative Temperature (RELT): In Thermometer mode, the RELT field of this 
register report the relative temperature of the thermal sensor. Provides a two's 
complement value of the thermal sensor relative to the Hot Trip Point. 
Temperature above the Hot Trip Point will be positive.
TR and HTPS can both vary between 0 and 255. But RELT will be clipped between 
±127 to keep it an 8 bit number.
See also TSS[Thermometer mode Output Valid]
In the Analog mode, the RELT field reports HTPS value. 
23:16
RW
00h
Aux0 Trip point setting (A0TPS): Sets the target for the Aux0 trip point.
15:8
RW/L
00h
Hot Trip Point Setting (HTPS): Sets the target value for the Hot trip point. 
Lockable via TCO bit 7.
7:0
RW/L
00h
Catastrophic Trip Point Setting (CTPS): Sets the target for the Catastrophic 
trip point. See also TST[Direct DAC Connect Test Enable].
Lockable via TCO bit 7.