Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート

製品コード

P4X-UPE3210-316-6M1333

Datasheet

Introduction

The Intel

3200 and 3210 Chipsets are designed for use with the Dual-Core Intel

Xeon

Processor 3000 Series and Quad-Core Intel

Xeon

Processor 3200 Series in

server platforms. The chipset contains two components: 3210/3100 MCH for the host

bridge and I/O Controller Hub 9 (ICH9) for the I/O subsystem. The ICH9 is the ninth

generation I/O Controller Hub and provides a multitude of I/O related functions.

show example system block diagrams for the Intel

3200 and

3210 Chipsets.

This document is the datasheet for the Intel

3200 and 3210 Memory Controller Hub

(MCH). Topics covered include; signal description, system memory map, PCI register

description, a description of the MCH interfaces and major functional units, electrical

characteristics, ballout definitions, and package characteristics.

Note:

Unless otherwise specified, ICH9 refers to the Intel

82801IB ICH9 and Intel

82801IR

ICH9R I/O Controller Hub 9 components.

Note:

The term ICH9 refers to the ICH9 and ICH9R components.

Note:

In this document, all references to MCH apply to both 3200 MCH and 3210 MCH, unless

otherwise noted.