Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート

190

Datasheet

B/D/F/Type:

0/1/0/MMR

Address Offset: 144–147h

Default Value:

02000100h

Access:

RO, RWO 

Size:

32 bits

This register provides information about the root complex element containing this Link 

Declaration Capability.

B/D/F/Type:

0/1/0/MMR

Address Offset: 150–153h

Default Value:

00000000h

Access:

RO, RWO 

Size:

32 bits

This register provides the first part of a Link Entry which declares an internal link to 

another Root Complex Element.

31:24

RO

02h

Port Number (PN): Specifies the port number associated with this element 
with respect to the component that contains this element. This port number 
value is utilized by the egress port of the component to provide arbitration to 
this Root Complex Element.

23:16

RWO

00h

Component ID (CID): Identifies the physical component that contains this 
Root Complex Element.

15:8

RO

01h

Number of Link Entries (NLE): Indicates the number of link entries following 
the Element Self Description. This field reports 1 (to Egress port only as we don't 
report any peer-to-peer capabilities in our topology).

7:4

RO

0h

Reserved 

3:0

RO

0h

Element Type (ET): Indicates Configuration Space Element.

31:24

RO

00h

Target Port Number (TPN): Specifies the port number associated with the 
element targeted by this link entry (Egress Port). The target port number is with 
respect to the component that contains this element as specified by the target 
component ID.

23:16

RWO

00h

Target Component ID (TCID): Identifies the physical or logical component 
that is targeted by this link entry.

15:2

RO

0000h

Reserved 

1

RO

0b

Link Type (LTYP): Indicates that the link points to memory-mapped space (for 
RCRB). The link address specifies the 64-bit base address of the target RCRB.

0

RWO

0b

Link Valid (LV): 
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.