Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート

Datasheet

21

• Supports maximum memory bandwidth of 6.4 GB/s in single-channel mode or 

12.8 GB/s in dual-channel mode assuming DDR2 800 MHz.

• Supports 512-Mb and 1-Gb DDR2 DRAM technologies for x8 and x16 devices.
• Using 512 Mb device technologies, the smallest memory capacity possible is 

256 MB, assuming Single Channel Mode with a single x16 single sided un-buffered 

non-ECC DIMM memory configuration. 

• Using 1 Gb device technologies, the largest memory capacity possible is 8 GB, 

assuming Dual Channel Mode with four x8 double sided un-buffered non-ECC or 

ECC DIMM memory configurations. 

Note: The ability to support greater than the largest memory capacity is subject to 

availability of higher density memory devices.

• Supports up to 32 simultaneous open pages per channel (assuming 4 ranks of 

8 bank devices)

• Supports opportunistic refresh scheme
• Supports Partial Writes to memory using Data Mask (DM) signals
• Supports a memory thermal management scheme to selectively manage reads 

and/or writes. Memory thermal management can be triggered either by on-die 

thermal sensor, or by preset limits. Management limits are determined by weighted 

sum of various commands that are scheduled on the memory interface.

Direct Media Interface (DMI) is the chip-to-chip connection between the MCH and 

ICH9. This high-speed interface integrates advanced priority-based servicing allowing 

for concurrent traffic and true isochronous transfer capabilities. Base functionality is 

completely software transparent permitting current and legacy software to operate 

normally.

To provide for true isochronous transfers and configurable Quality of Service (QoS) 

transactions, the ICH9 supports two virtual channels on DMI: VC0 and VC1. These two 

channels provide a fixed arbitration scheme where VC1 is always the highest priority. 

VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be 

specifically enabled and configured at both ends of the DMI link (i.e., the ICH9 and 

MCH).

• A chip-to-chip connection interface to Intel ICH9 
• 2 GB/s point-to-point DMI to ICH9 (1 GB/s each direction)
• 100 MHz reference clock (shared with PCI Express)
• 32-bit downstream addressing
• APIC and MSI interrupt messaging support. Will send Intel-defined “End Of 

Interrupt” broadcast message when initiated by the processor.

• Message Signaled Interrupt (MSI) messages
• SMI, SCI, and SERR error indication