Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート

Datasheet

211

B/D/F/Type:

0/3/3/KT MM/IO

Address Offset: 5h

Default Value:

00h

Access:

RO, RO/CR 

Size:

8 bits

This register provides status information of the data transfer to the Host. Error 

indication, etc., are provided by the hardware(HW)/firmware(FW) to the host via this 

register. 

Reset: Host system reset or D3->D0 transition.

7

RO

0b

RX FIFO Error (RXFER): This bit is cleared in non FIFO mode. Bit is connected 
to the BI bit in FIFO mode.

6

RO

0b

Transmit Shift Register Empty (TEMT): This bit is connected by hardware to 
bit 5 (THRE) of this register

5

RO

0b

Transmit Holding Register Empty (THRE): The bit is always set when the 
mode (FIFO/Non-FIFO) is changed by the Host. This bit is active only when the 
THR operation is enabled by the FW. 
This bit has acts differently in the different modes: 

• Non FIFO Mode: This bit is cleared by 

hardware

 when the Host writes to the THR 

registers and set by 

hardware 

when the FW reads the THR register.

• FIFO Mode: This bit is set by 

hardware

 when the THR FIFO is empty, and cleared by 

hardware

 when the THR FIFO is not empty.

This bit is reset on Host system reset or D3->D0 transition. 

4

RO/CR

0b

Break Interrupt (BI): This bit is cleared by hardware when the LSR register is 
being read by the Host.
This bit is set by hardware in two cases: 

• FIFO Mode: The FW sets the BI bit by setting the SBI bit in the KTRIVR register (See 

KT AUX registers)

• Non FIFO Mode: the FW sets the BI bit by setting the BIA bit in the KTRxBR register 

(see KT AUX registers)

3:2

RO

00b

Reserved 

1

RO/CR

0b

Overrun Error (OE): This bit is cleared by hardware when the LSR register is 
being read by the Host. The FW typically sets this bit, but it is cleared by 
hardware when the host reads the LSR.

0

RO

0b

• Non-FIFO Mode: This bit is set when the FW writes to the RBR register and cleared by 

hardware when the RBR register is being Read by the Host.

• FIFO Mode: This bit is set by hardware when the RBR FIFO is not empty and cleared by 

hardware when the RBR FIFO is empty.

This bit is reset on Host System Reset or D3->D0 transition