Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート
製品コード
P4X-UPE3210-316-6M1333
Datasheet
223
Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
8.14
SSTS1—Secondary Status
B/D/F/Type:
0/6/0/PCI
Address Offset: 1E–1Fh
Default Value:
0000h
Access:
RO, RWC
Size:
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side of the "virtual" PCI-PCI bridge embedded within MCH.
Bit
Access
Default
Value
Description
15
RWC
0b
Detected Parity Error (DPE): This bit is set by the Secondary Side for a Type 1
Configuration Space header device whenever it receives a Poisoned Transaction
Layer Packet, regardless of the state of the Parity Error Response Enable bit in
the Bridge Control Register.
Configuration Space header device whenever it receives a Poisoned Transaction
Layer Packet, regardless of the state of the Parity Error Response Enable bit in
the Bridge Control Register.
14
RWC
0b
Received System Error (RSE): This bit is set when the Secondary Side for a
Type 1 configuration space header device receives an ERR_FATAL or
ERR_NONFATAL.
Type 1 configuration space header device receives an ERR_FATAL or
ERR_NONFATAL.
13
RWC
0b
Received Master Abort (RMA): This bit is set when the Secondary Side for
Type 1 Configuration Space Header Device (for requests initiated by the Type 1
Header Device itself) receives a Completion with Unsupported Request
Completion Status.
Type 1 Configuration Space Header Device (for requests initiated by the Type 1
Header Device itself) receives a Completion with Unsupported Request
Completion Status.
12
RWC
0b
Received Target Abort (RTA): This bit is set when the Secondary Side for
Type 1 Configuration Space Header Device (for requests initiated by the Type 1
Header Device itself) receives a Completion with Completer Abort Completion
Status.
Type 1 Configuration Space Header Device (for requests initiated by the Type 1
Header Device itself) receives a Completion with Completer Abort Completion
Status.
11
RO
0b
Signaled Target Abort (STA): Not Applicable or Implemented. Hardwired to 0.
The MCH does not generate Target Aborts (the MCH will never complete a
request using the Completer Abort Completion status).
The MCH does not generate Target Aborts (the MCH will never complete a
request using the Completer Abort Completion status).
10:9
RO
00b
DEVSELB Timing (DEVT): Not Applicable or Implemented. Hardwired to 0.
8
RWC
0b
Master Data Parity Error (SMDPE): When set, indicates that the MCH
received across the link (upstream) a Read Data Completion Poisoned
Transaction Layer Packet (EP=1). This bit can only be set when the Parity Error
Enable bit in the Bridge Control register is set.
received across the link (upstream) a Read Data Completion Poisoned
Transaction Layer Packet (EP=1). This bit can only be set when the Parity Error
Enable bit in the Bridge Control register is set.
7
RO
0b
Fast Back-to-Back (FB2B): Not Applicable or Implemented. Hardwired to 0.
6
RO
0b
Reserved
5
RO
0b
66/60 MHz capability (CAP66): Not Applicable or Implemented. Hardwired to
0.
0.
4:0
RO
00h
Reserved