Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート
製品コード
P4X-UPE3210-316-6M1333
Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
226
Datasheet
8.17
PMBASE1—Prefetchable Memory Base Address
Upper
B/D/F/Type:
0/6/0/PCI
Address Offset: 24–25h
Default Value:
FFF1h
Access:
RW, RO
Size:
16 bits
This register in conjunction with the corresponding Upper Base Address register
controls the processor to PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1 MB boundary.
Bit
Access
Default
Value
Description
15:4
RW
FFFh
Prefetchable Memory Base Address (MBASE): Corresponds to A[31:20] of
the lower limit of the memory range that will be passed to PCI Express.
the lower limit of the memory range that will be passed to PCI Express.
3:0
RO
1h
64-bit Address Support: Indicates that the upper 32 bits of the prefetchable
memory region base address are contained in the Prefetchable Memory base
Upper Address register at 28h.
memory region base address are contained in the Prefetchable Memory base
Upper Address register at 28h.