Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート
製品コード
P4X-UPE3210-316-6M1333
Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
246
Datasheet
8.42
SLOTCTL—Slot Control
B/D/F/Type:
0/6/0/PCI
Address Offset: B8–B9h
Default Value:
0000h
Access:
RO, RW
Size:
16 bits
PCI Express Slot related registers.
3
RO
0b
Attention Indicator Present (AIP): When set to 1b, this bit indicates that an
Attention Indicator is electrically controlled by the chassis.
Attention Indicator is electrically controlled by the chassis.
2
RO
0b
MRL Sensor Present (MSP): When set to 1b, this bit indicates that an MRL
Sensor is implemented on the chassis for this slot.
Sensor is implemented on the chassis for this slot.
1
RO
0b
Power Controller Present (PCP): When set to 1b, this bit indicates that a
software programmable Power Controller is implemented for this slot/adapter
(depending on form factor).
software programmable Power Controller is implemented for this slot/adapter
(depending on form factor).
0
RO
0b
Attention Button Present (ABP): When set to 1b, this bit indicates that an
Attention Button for this slot is electrically controlled by the chassis.
Attention Button for this slot is electrically controlled by the chassis.
Bit
Access
Default
Value
Description
Bit
Access
Default
Value
Description
15:13
RO
000b
Reserved
12
RO
0b
Data Link Layer State Changed Enable (DLLSCE): If the Data Link Layer
Link Active capability is implemented, when set to 1b, this field enables software
notification when Data Link Layer Link Active field is changed.
If the Data Link Layer Link Active capability is not implemented, this bit is
permitted to be read-only with a value of 0b.
Link Active capability is implemented, when set to 1b, this field enables software
notification when Data Link Layer Link Active field is changed.
If the Data Link Layer Link Active capability is not implemented, this bit is
permitted to be read-only with a value of 0b.
11
RO
0b
Electromechanical Interlock Control (EIC): If an Electromechanical
Interlock is implemented, a write of 1b to this field causes the state of the
interlock to toggle. A write of 0b to this field has no effect. A read to this register
always returns a 0.
Interlock is implemented, a write of 1b to this field causes the state of the
interlock to toggle. A write of 0b to this field has no effect. A read to this register
always returns a 0.
10
RO
0b
Power Controller Control (PCC): If a Power Controller is implemented, this
field when written sets the power state of the slot per the defined encodings.
Reads of this field must reflect the value from the latest write, unless software
issues a write without waiting for the previous command to complete in which
case the read value is undefined.
Depending on the form factor, the power is turned on/off either to the slot or
within the adapter. Note that in some cases the power controller may
autonomously remove slot power or not respond to a power-up request based on
a detected fault condition, independent of the Power Controller Control setting.
0 = Power On
1 = Power Off
If the Power Controller Implemented field in the Slot Capabilities register is set
to 0b, then writes to this field have no effect and the read value of this field is
undefined.
field when written sets the power state of the slot per the defined encodings.
Reads of this field must reflect the value from the latest write, unless software
issues a write without waiting for the previous command to complete in which
case the read value is undefined.
Depending on the form factor, the power is turned on/off either to the slot or
within the adapter. Note that in some cases the power controller may
autonomously remove slot power or not respond to a power-up request based on
a detected fault condition, independent of the Power Controller Control setting.
0 = Power On
1 = Power Off
If the Power Controller Implemented field in the Slot Capabilities register is set
to 0b, then writes to this field have no effect and the read value of this field is
undefined.