Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート

Datasheet

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This chapter provides a detailed description of MCH signals. The signals are arranged in 

functional groups according to their associated interface. 

The following notations are used to describe the signal type.

PCI Express*

PCI Express interface signals. These signals are compatible with PCI Express 1.1 
Signaling Environment AC Specifications and are AC coupled. The buffers are 
not 3.3 V tolerant. Differential voltage spec = (|D+ – D-|) * 2 = 1.2 Vmax. 
Single-ended maximum = 1.25 V. Single-ended minimum = 0 V.

DMI

Direct Media Interface signals. These signals are compatible with PCI Express 
1.1 Signaling Environment AC Specifications, but are DC coupled. The buffers 
are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) * 2 = 1.2 Vmax. 
Single-ended maximum = 1.25 V. Single-ended minimum = 0 V.

CMOS

CMOS buffers. 1.5 V tolerant.

COD

CMOS Open Drain buffers. 3.3 V tolerant. 

HVCMOS

High Voltage CMOS buffers. 3.3 V tolerant.

HVIN

High Voltage CMOS input-only buffers. 3.3 V tolerant.

SSTL_1.8

Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V 
tolerant.

A

Analog reference or output. May be used as a threshold voltage or for buffer 
compensation.

GTL+

Gunning Transceiver Logic signaling technology. Implements a voltage level as 
defined by V

TT

 of 1.2 V and/or 1.1 V.