Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート

Datasheet

275

There are several registers that need to be configured to support the MCH thermal 

sensor functionality and SMI# generation. Customers must enable the Catastrophic 

Trip Point as protection for the MCH. If the Catastrophic Trip Point is crossed, then the 

MCH will instantly turn off all clocks inside the device. Customers may optionally enable 

the Hot Trip Point to generate SMI #. Customers will be required to then write their own 

SMI# handler in BIOS that will speed up the MCH (or system) fan to cool the part.

The SMICMD register requires that a bit be set to generate an SMI# when the Hot Trip 

point is crossed. The ERRSTS register can be inspected for the SMI alert.

The Digital Thermometer Configuration Registers reside in the MCHBAR configuration 

space.

Error Status

ERRSTS

C8

C9

0000h

RWC/S, RO 

SMI Command

SMICMD

CC

CD

0000h

RO, RW 

Thermal Sensor Control 1

TSC1

CD8

CD8

00h

RW/L, RW, 

RS/WC 

Thermal Sensor Control 2

TSC2

CD9

CD9

00h

RO, RW/L 

Thermal Sensor Status

TSS

CDA

CDA

00h

RO 

Thermal Sensor Temperature Trip 
Point

TSTTP

CDC

CDF

00000000h

RO, RW, RW/L 

Thermal Calibration Offset

TCO

CE2

CE2

00h

RW/L/K, RW/L 

Hardware Throttle Control

THERM1

CE4

CE4

00h

RW/L, RO, 

RW/L/K 

TCO Fuses

THERM3

CE6

CE6

00h

RO, RS/WC 

Thermal Interrupt Status

TIS

CEA

CEB

0000h

RO, RWC 

Thermal SMI Command

TSMICMD

CF1

CF1

00h

RO, RW