Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート
製品コード
P4X-UPE3210-316-6M1333
Datasheet
61
MCH Register Description
4.4.1
Internal Device Configuration Accesses
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus #0 device.
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus #0 device.
If the targeted PCI Bus 0 device exists in the MCH and is not disabled, the configuration
cycle is claimed by the appropriate device.
cycle is claimed by the appropriate device.
Figure 10.
MCH Configuration Cycle Flow Chart
DW I/O Write to
CONFIG_ADDRESS
with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
MCH Generates
Type 1 Access
to PCI Express
MCH allows cycle
to
go to DMI resulting
in Master Abort
Bus# > SEC BUS
Bus#
Bus#
≤ SUB BUS
in MCH Dev 1
Bus# = 0
Device# = 1 &
Dev # 1 Enabled
& Function# = 0
& Function# = 0
Device# = 0 &
Function# = 0
Function# = 0
MCH Generates
DMI Type 1
Configuration Cycle
Bus# =
SECONDARYBUS
in MCH Dev 1
MCH Claims
MCH Claims
Yes
No
Yes
Yes
No
No
Yes
Yes
No
No
Device# = 0
MCH Generates
Type 0 Access
to PCI Express
Yes
MCH Generates
DMI Type 0
Configuration Cycle
No