Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート
製品コード
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
68
Datasheet
5.1.3
PCICMD—PCI Command
B/D/F/Type:
0/0/0/PCI
Address Offset: 4–5h
Default Value:
0006h
Access:
RO, RW
Size:
16 bits
Since MCH Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
Bit
Access
Default
Value
Description
15:9
RO
00h
Reserved
8
RW
0b
SERR Enable (SERRE): This bit is a global enable bit for Device 0 (and Device
6 for the 3210 MCH) SERR messaging. The MCH does not have an SERR signal.
The MCH communicates the SERR condition by sending an SERR message over
DMI to the ICH.
1 = The MCH is enabled to generate SERR messages over DMI for specific
6 for the 3210 MCH) SERR messaging. The MCH does not have an SERR signal.
The MCH communicates the SERR condition by sending an SERR message over
DMI to the ICH.
1 = The MCH is enabled to generate SERR messages over DMI for specific
Device 0 error conditions that are individually enabled in the ERRCMD and
DMIUEMSK registers. The error status is reported in the ERRSTS, PCISTS,
and DMIUEST registers.
DMIUEMSK registers. The error status is reported in the ERRSTS, PCISTS,
and DMIUEST registers.
0 = The SERR message is not generated by the MCH for Device 0.
Note that this bit only controls SERR messaging for the Device 0. Device 1 has
its own SERRE bits to control error reporting for error conditions occurring in
that device. The control bits are used in a logical OR manner to enable the SERR
DMI message mechanism.
Note that this bit only controls SERR messaging for the Device 0. Device 1 has
its own SERRE bits to control error reporting for error conditions occurring in
that device. The control bits are used in a logical OR manner to enable the SERR
DMI message mechanism.
7
RO
0b
Address/Data Stepping Enable (ADSTEP): Address/data stepping is not
implemented in the MCH, and this bit is hardwired to 0. Writes to this bit
position have no effect.
implemented in the MCH, and this bit is hardwired to 0. Writes to this bit
position have no effect.
6
RW
0b
Parity Error Enable (PERRE): Controls whether or not the Master Data Parity
Error bit in the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
Error bit in the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
5
RO
0b
Reserved
4
RO
0b
Memory Write and Invalidate Enable (MWIE): The MCH will never issue
memory write and invalidate commands. This bit is therefore hardwired to 0.
Writes to this bit position will have no effect.
memory write and invalidate commands. This bit is therefore hardwired to 0.
Writes to this bit position will have no effect.
3
RO
0b
Reserved
2
RO
1b
Bus Master Enable (BME): The MCH is always enabled as a master on the
backbone. This bit is hardwired to a "1". Writes to this bit position have no
effect.
backbone. This bit is hardwired to a "1". Writes to this bit position have no
effect.
1
RO
1b
Memory Access Enable (MAE): The MCH always allows access to main
memory. This bit is not implemented and is hardwired to 1. Writes to this bit
position have no effect.
memory. This bit is not implemented and is hardwired to 1. Writes to this bit
position have no effect.
0
RO
0b
I/O Access Enable (IOAE): This bit is not implemented in the MCH and is
hardwired to a 0. Writes to this bit position have no effect.
hardwired to a 0. Writes to this bit position have no effect.