Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート

94

Datasheet

B/D/F/Type:

0/0/0/PCI

Address Offset: CC–CDh

Default Value:

0000h

Access:

RO, RW 

Size:

16 bits

This register enables various errors to generate an SMI DMI special cycle. When an 

error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI 

special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers, 

respectively. Note that one and only one message type can be enabled.

B/D/F/Type:

0/0/0/PCI

Address Offset: DC–DFh

Default Value:

00000000h

Access:

RW 

Size:

32 bits

This register holds 32 writable bits with no functionality behind them. It is for the 

convenience of BIOS drivers.

15:12

RO

0h

Reserved

11

RW

0b

SMI on MCH Thermal Sensor Trip (TSTSMI): 
1 = A SMI DMI special cycle is generated by MCH when the thermal sensor trip 

requires an SMI. A thermal sensor trip point cannot generate more than one 
special cycle.

0 = Reporting of this condition via SMI messaging is disabled.

10:2

RO

000h

Reserved

1

RW

0b

SMI on Multiple-Bit DRAM ECC Error (DMESMI): 
1 = The MCH generates an SMI DMI message when it detects a multiple-bit error 

reported by the DRAM controller.

0 = Reporting of this condition via SMI messaging is disabled. For systems not 

supporting ECC this bit must be disabled.

0

RW

0b

SMI on Single-bit ECC Error (DSESMI): 
1 = The MCH generates an SMI DMI special cycle when the DRAM controller 

detects a single bit error.

0 = Reporting of this condition via SMI messaging is disabled. For systems that 

do not support ECC this bit must be disabled.

31:0

RW

0000000

0h

Scratchpad Data (SKPD): 1 DWord of data storage.