Renesas R5S72643 ユーザーズマニュアル

 

Section 25   NAND Flash Memory Controller 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1309 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

8 STERB 

0 

R/(W)* Status Error 

Indicates the result of status read. This bit is set to 1 if 
the specific bit in the bits STAT[7:0] in FLBSYCNT is 
set to 1 in status read. 

This bit is a flag. 1 cannot be written to this bit. Only 0 
can be written to clear the flag. 

0: Indicates that no status error occurs (the specific bit 

in the bits STAT[7:0] in FLBSYCNT is 0.) 

1: Indicates that a status error occurs 

For details on the specific bit in STAT7 to STAT0 bits, 
see section 25.4.7, Status Read. 

7 BTOERB 

0 

R/(W)* R/

B Timeout Error 

This bit is set to 1 if an R/

B timeout error occurs (the 

bits RBTIMCNT[19:0] in FLBSYCNT are decremented 
to 0). 

This bit is a flag. 1 cannot be written to this bit. Only 0 
can be written to clear the flag. 

0: Indicates that no R/

B timeout error occurs 

1: Indicates that an R/

B timeout error occurs 

6 TRREQF1 

0 

R/(W)* FLECFIFO Transfer Request Flag 

Indicates that a transfer request is issued from 
FLECFIFO. 

This bit is a flag. 1 cannot be written to this bit. Only 0 
can be written to clear the flag. 

0: Indicates that no transfer request is issued from 

FLECFIFO 

1: Indicates that a transfer request is issued from 

FLECFIFO