Renesas R5S72643 ユーザーズマニュアル

R01UH0134EJ0400  Rev. 4.00  

 

Page 2065 of 2108 

Sep 24, 2014 

 

 

Main Revisions for This Edition 

1.1   Block Diagram 

 

1 Description 

amended 

The CPU in this LSI is an SH-2A CPU, which provides 
upward compatibility for SH-1, SH-2, and SH-2E CPUs at 
object code level. It has a RISC-type instruction set, 
superscalar architecture, and Harvard architecture, for 
superior rates of instruction execution. In addition, an 
independent 32-bit internal-bus architecture  

 

enhances data processing power. This CPU brings the 
user the ability to set up high-performance systems with 
strong functionality at less expense than was achievable 
with previous microcontrollers, and is even able to handle 
realtime control applications requiring high-speed 
characteristics. 

Table 1.1   SH7262/7264 
Features 

5 Table 

amended 

Realtime clock 

• Internal clock, calendar function, alarm function 
• Interrupts can be generated at intervals of 1/64 s by the 32.768-kHz 

on-chip crystal oscillator 

 

1.5   Pin Functions 

Table 1.3   Pin Functions 

23 Table 

amended 

Multi-function 
timer pulse unit 
2  

TCLKA, 
TCLKB, 
TCLKC, 
TCLKD 

I Timer 

clock 

input External clock input pins for the 

timer. 

TIOC4A, 
TIOC4B, 
TIOC4C, 
TIOC4D 

I/O Input capture/ 

output compare 
(channel 4) 

The TGRA_4 to TGRD_4 input 
capture input/output compare 
output/PWM output pins. 

Figure 1.3 (2)   Simplified 
Circuit Diagram (TTL AND 
Input Buffer) 

44 Figure 

amended 

PAD

TTL input data

TTL input enable