Renesas R5S72643 ユーザーズマニュアル

 

Section 15   Serial Communication Interface with FIFO 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 725 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

7 ER  0 R/(W)* Receive Error 

Indicates the occurrence of a framing error, or of a 
parity error when receiving data that includes parity.*

1

0: Receiving is in progress or has ended normally 

[Clearing conditions] 

  ER is cleared to 0 a power-on reset 
  ER is cleared to 0 when the chip is when 0 is 

written after 1 is read from ER 

1: A framing error or parity error has occurred. 

[Setting conditions] 

  ER is set to 1 when the stop bit is 0 after checking 

whether or not the last stop bit of the received 

data is 1 at the end of one data receive 

operation*

2

 

  ER is set to 1 when the total number of 1s in the 

receive data plus parity bit does not match the 

even/odd parity specified by the O/

E bit in SCSMR

Notes:  1.  Clearing the RE bit to 0 in SCSCR does 

not affect the ER bit, which retains its 
previous value. Even if a receive error 
occurs, the receive data is transferred to 
SCFRDR and the receive operation is 
continued. Whether or not the data read 
from SCFRDR includes a receive error 
can be detected by the FER and PER bits 
in SCFSR.  

 

2.  In two stop bits mode, only the first stop 

bit is checked; the second stop bit is not 
checked.