Intermec 6100 参照ガイド

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Not all status bit values of the PCĆcompatible UARTs are supported.
Break conditions are not generated or detected.
Sticky parity is not supported.
The transmit shift register empty and break detect signals are not available.
The transmit shift register empty and transmit holding register bits are both set

when the UART is ready.
The carrier detect, ring indicator, delta carrier detect, trailingĆedge ring indicaĆ

tor, delta data set ready, and delta clearĆtoĆsend signals are not available.

Subfunction 1, of Interrupt 15h, is traditionally reserved for cassette interface

control.  The 4000 Series BIOS replaced it with a set of multitasking services inĆ

formally referred to as INT15.  4000API.EXE provides this same set of services

for 4000 Series multitasking applications.  These services are nonstandard, but

4000API.EXE may be executed on any PC to provide these services.

Int15 manipulates two linked lists of task contexts, the ready list and the pended

list.  The pended list contains tasks that are waiting for some event.  A task

moves from this list to the ready list when its timeout expires or when the event

on which it is waiting occurs.
The ready list is a queue of tasks scheduled for execution.  Tasks enter at the tail

of the queue and are activated from the head.  All tasks have the same priority

and are executed roundĆrobin.
The currently executing task is not on either list.  It moves to the pended list if it

issues wait any," pend on mailbox, pend on queue, or delay with timeout comĆ

mands.  The current task moves to the ready list if its time slice expires (preempĆ

tive only) or if it voluntarily gives up control by issuing a delay with 0 timeout.
Int15 defaults to cooperative multitasking.  That means that every task must

occasionally give up control of the processor to let other tasks execute.
By enabling timeĆslicing, int15 becomes a preemptive multitasker.  Each task in

the ready list is allocated a 55Ćmillisecond time slice.  If the currently executing

task exhausts its time slice before relinquishing control of the processor, it is forĆ

cibly swapped out and placed on the tail of the ready list.

Functions that require timeout values as input expect the register pair DXCX to

contain the number of milliseconds before timeout.  The timer resolution is the

same as the system timer ticks:  55 milliseconds.  A task that requests a one milĆ

lisecond time out is guaranteed to wait at least one millisecond and possibly up

to 55 milliseconds.

Most of the BIOS device handling services are not reentrant.  Tasks cannot share

the same device (the display, for example) without an arbitrator that ensures

that both tasks do not try to use the BIOS at the same time.
This resource arbitration can be handled via the intertask communication proĆ

vided by mailboxes and queues.