Intel Xeon X3460 BX80605X3460 ユーザーズマニュアル

製品コード

BX80605X3460

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

Contents

Introduction ............................................................................................................ 17
1.1

Configuration Process and Registers ....................................................................... 19
2.1

Platform Configuration Structure ......................................................................... 19
2.1.1

Processor Integrated I/O (IIO) Devices (PCI Bus 0) .................................... 19

2.1.2

Processor Uncore Devices (PCI Bus — FFh) ................................................ 20

2.2

Configuration Mechanisms .................................................................................. 21
2.2.1

Standard PCI Express* Configuration Mechanism........................................ 21

2.2.2

PCI Express* Configuration Mechanism ..................................................... 21

2.3

Routing Configuration Accesses ........................................................................... 23
2.3.1

Internal Device Configuration Accesses ..................................................... 24

2.3.2

Bridge-Related Configuration Accesses ...................................................... 24
2.3.2.1

PCI Express* Configuration Accesses ........................................... 24

2.3.2.2

DMI Configuration Accesses ....................................................... 25

2.4

Processor Register Introduction........................................................................... 25

2.5

I/O Mapped Registers ........................................................................................ 26

Processor Integrated I/O (IIO) Configuration Registers ......................................... 27
3.1

Processor IIO Devices (PCI Bus 0) ....................................................................... 27

3.2

Device Mapping................................................................................................. 28
3.2.1

Unimplemented Devices/Functions and Registers........................................ 28

3.3

PCI Express*/DMI Configuration Registers ............................................................ 28
3.3.1

Other Register Notes .............................................................................. 28

3.3.2

Configuration Register Map...................................................................... 29

3.3.3

Standard PCI Configuration Space (0h to 3Fh) —

Type 0/1 Common Configuration Space..................................................... 34
3.3.3.1

VID—Vendor Identification Register............................................. 34

3.3.3.2

DID—Device Identification Register ............................................. 34

3.3.3.3

PCICMD—PCI Command Register ................................................ 35

3.3.3.4

PCISTS—PCI Status Register ...................................................... 37

3.3.3.5

RID—Revision Identification Register ........................................... 39

3.3.3.6

CCR—Class Code Register .......................................................... 39

3.3.3.7

CLSR—Cacheline Size Register.................................................... 40

3.3.3.8

PLAT—Primary Latency Timer ..................................................... 40

3.3.3.9

HDR—Header Type Register ....................................................... 40

3.3.3.10 SVID—Subsystem Vendor ID ...................................................... 41

3.3.3.11 SID—Subsystem Identity ........................................................... 41

3.3.3.12 CAPPTR—Capability Pointer ........................................................ 41

3.3.3.13 INTLIN—Interrupt Line Register .................................................. 41

3.3.3.14 INTPIN—Interrupt Pin Register ................................................... 42

3.3.3.15 PBUS—Primary Bus Number Register........................................... 42

3.3.3.16 SECBUS—Secondary Bus Number ............................................... 42

3.3.3.17 SUBBUS—Subordinate Bus Number Register................................. 43

3.3.3.18 IOBAS—I/O Base Register.......................................................... 43

3.3.3.19 IOLIM—I/O Limit Register .......................................................... 44

3.3.3.20 SECSTS—Secondary Status Register ........................................... 45

3.3.3.21 MBAS—Memory Base ................................................................ 46

3.3.3.22 MLIM—Memory Limit ................................................................. 46

3.3.3.23 PMBASE—Prefetchable Memory Base Register............................... 47

3.3.3.24 PMLIMIT—Prefetchable Memory Limit .......................................... 47

3.3.3.25 PMBASEU—Prefetchable Memory Base (Upper 32 bits) ................... 48

3.3.3.26 PMLIMITU—Prefetchable Memory Limit (Upper 32 bits) .................. 48

3.3.3.27 BCTRL—Bridge Control Register .................................................. 48

3.3.4

Device-Specific PCI Configuration Space — 40h to FFh ................................ 50
3.3.4.1

SCAPID—Subsystem Capability Identity ....................................... 50