Intel Xeon X3460 BX80605X3460 ユーザーズマニュアル
製品コード
BX80605X3460
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
25
Configuration Process and Registers
2.3.2.2
DMI Configuration Accesses
Accesses to disabled processor internal devices, bus numbers not claimed by the Host-
PCI Express bridge, or PCI Bus 0 devices not part of the processor will subtractively
decode to the PCH and consequently be forwarded over the DMI using a PCI Express
configuration TLP. In
PCI Express bridge, or PCI Bus 0 devices not part of the processor will subtractively
decode to the PCH and consequently be forwarded over the DMI using a PCI Express
configuration TLP. In
, the subtractive decode is completed by testing Devices
0 through n, where Devices 0 through n, if enabled and Function 0 is present in the
processor are claimed by the processor.
processor are claimed by the processor.
If the Bus Number is zero, the processor will generate a Type 0 Configuration Cycle TLP
on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the
Host-PCI Express bridge, the processor will generate a Type 1 Configuration Cycle TLP
on DMI.
on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the
Host-PCI Express bridge, the processor will generate a Type 1 Configuration Cycle TLP
on DMI.
The PCH routes configurations accesses in a manner similar to the processor. The PCH
decodes the configuration TLP and generates a corresponding configuration access.
Accesses targeting a device on PCI Bus 0 may be claimed by an internal device. The
PCH compares the non-zero Bus Number with the Secondary Bus Number and
Subordinate Bus Number registers of its PCI-to-PCI bridges to determine if the
configuration access is meant for Primary PCI, or some other downstream PCI bus or
PCI Express link.
decodes the configuration TLP and generates a corresponding configuration access.
Accesses targeting a device on PCI Bus 0 may be claimed by an internal device. The
PCH compares the non-zero Bus Number with the Secondary Bus Number and
Subordinate Bus Number registers of its PCI-to-PCI bridges to determine if the
configuration access is meant for Primary PCI, or some other downstream PCI bus or
PCI Express link.
Configuration accesses that are forwarded to the PCH, but remain unclaimed by any
device or bridge will result in a master abort.
device or bridge will result in a master abort.
2.4
Processor Register Introduction
The processor contains two sets of software accessible registers – control registers and
internal configuration registers:
internal configuration registers:
• Control registers are I/O mapped into the processor I/O space, which control
, I/O Mapped
Registers).
• Internal configuration registers residing within the processor are partitioned into
the device register sets as indicated in
and
The processor internal registers (I/O Mapped, Configuration and PCI Express Extended
Configuration registers) are accessible by the Host processor. The registers that reside
within the lower 256 bytes of each device can be accessed as byte, word (16 bit), or
DWord (32 bit) quantities, with the exception of CONFIG_ADDRESS, which can only be
accessed as a DWord. All multi-byte numeric fields use "little-endian" ordering (that is,
lower addresses contain the least significant parts of the field). Registers which reside
in bytes 256 through 4095 of each device may only be accessed using memory mapped
transactions in DWord (32 bit) quantities.
Configuration registers) are accessible by the Host processor. The registers that reside
within the lower 256 bytes of each device can be accessed as byte, word (16 bit), or
DWord (32 bit) quantities, with the exception of CONFIG_ADDRESS, which can only be
accessed as a DWord. All multi-byte numeric fields use "little-endian" ordering (that is,
lower addresses contain the least significant parts of the field). Registers which reside
in bytes 256 through 4095 of each device may only be accessed using memory mapped
transactions in DWord (32 bit) quantities.
Some of the processor registers described in this section contain reserved bits; these
bits are labeled "Reserved”. Software must not modify reserved fields. On reads,
software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and
then written back. Note that the software does not need to perform read, merge, and
write operation for the Configuration Address Register.
bits are labeled "Reserved”. Software must not modify reserved fields. On reads,
software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and
then written back. Note that the software does not need to perform read, merge, and
write operation for the Configuration Address Register.