Intel L5618 AT80614005079AB ユーザーズマニュアル
製品コード
AT80614005079AB
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
161
Features
8
Features
8.1
Power-On Configuration (POC)
Several configuration options can be configured by hardware. Power-On configuration
(POC) functionality is either MUx’ed onto VID signals (see
(POC) functionality is either MUx’ed onto VID signals (see
) or
sampled on the active-to-inactive transition of RESET#. For specifics on these options,
please refer to
please refer to
Please note that requests to execute Built-In Self Test (BIST) are not selected by
hardware, but rather passed across the Intel QuickPath Interconnect link during
initialization.
hardware, but rather passed across the Intel QuickPath Interconnect link during
initialization.
Note:
1.
FRB = Fault-Resilient Boot
Table 8-1.
Power-On Configuration Signal Options
Configuration Option
Signal
Figure
Output tri-state
PROCHOT#
1
Notes:
1. Asserting the signal during RESET# de-assertion will select the corresponding option. Once selected, this
option cannot be changed except via another reset. The processor does not distinguish between a “warm”
reset and a “power-on” reset. Output tri-state via the PROCHOT# power-on configuration option is referred
to as Fault Resilient Boot (FRB).
PECI_ID#
PECI_ID#
2
2. Latched when VTTPWRGOOD is asserted and all internal power good conditions are met.
Assertion of the PROCHOT# signal through RESET# de-assertion (also referred to as
Fault Resilient Boot (FRB)) will tri-state processor outputs.
Fault Resilient Boot (FRB)) will tri-state processor outputs.
outlines timing
requirements when utilizing PROCHOT# as a power-on configuration option. In the
event an FRB is desired, PROCHOT# and RESET# should be asserted simultaneously.
Furthermore, once asserted, PROCHOT# should remain low long enough to meet the
TH: Power-On Configuration Hold Time (PROCHOT#) as outlined in
event an FRB is desired, PROCHOT# and RESET# should be asserted simultaneously.
Furthermore, once asserted, PROCHOT# should remain low long enough to meet the
TH: Power-On Configuration Hold Time (PROCHOT#) as outlined in
. Failure
to do so may result in false tri-state.
Market Segment Identification (MSID)
VID[2:0] / MSID[2:0]
2
Current Sensor Configuration (CSC)
VID[5:3] / CSC[2:0]
2
Figure 8-1. PROCHOT# POC Timing Requirements
CPURESET#
Tri-State POC
(xxPROCHOT#)
BCLK
Min Hold (106)
Min Setup (2)
xxPROCHOT# deassertion is not required for FRB
Non-FRB assertion of
xxPROCHOT# during this window
can trigger false tri-state