Intel MFS5520VI ユーザーズマニュアル

ページ / 56
Intel® Compute Module MFS5520VI TPS  
Functional Architecture 
Revision 1.3 
 
17 
Intel order number: E64311-005 
3.3  Intel
®
 5520 Chipset IOH 
The Intel
®
 5520 Chipset component is an I/O Hub (IOH.) The Intel
®
 5520 Chipset IOH provides 
a connection point between various I/O components and Intel processors through the Intel
®
 QPI 
interface.  
The Intel
®
 5520 Chipset IOH is capable of interfacing with up to 36 PCI Express* lanes, which 
can be configured in various combinations of x4, x8, x16, and limited x2 and x1 devices.  
The Intel
®
 5520 Chipset IOH is responsible for providing a path to the legacy bridge. In addition, 
the Intel
®
 5520 Chipset supports a x4 DMI (Direct Media Interface) link interface for the legacy 
bridge, and interfaces with other devices through SMBus, Controller Link, and RMII 
manageability interfaces. The Intel
®
 5520 Chipset supports the following features and 
technologies: 
ƒ
 
Intel
®
 QuickPath Interconnect (Intel
®
 QPI) 
ƒ
 
PCI Express* Gen2 
ƒ
 
Intel
®
 I/O Acceleration Technology 2 (Intel
®
 I/OAT2) 
ƒ
 
Intel
®
 Virtualization Technology (Intel
®
 VT) for Directed I/O 2 (Intel
®
 VT-d2) 
3.4  Intel
®
 82801JR I/O Controller Hub (ICH10R) 
The Intel
®
 82801JR I/O Controller Hub (ICH10R) provides extensive I/O support and provides 
the following functions and capabilities: 
ƒ
 
PCI Express* Base Specification, Revision 1.1 support 
ƒ
 
PCI Local Bus Specification, Revision 2.3 support for 33-MHz PCI operations (supports 
up to four REQ#/GNT# pairs) 
ƒ
 
ACPI Power Management Logic Support, Revision 3.0a 
ƒ
 
Enhanced DMA controller, interrupt controller, and timer functions 
ƒ
 
Integrated Serial ATA host controllers with independent DMA operation on up to six 
ports and AHCI support 
ƒ
 
USB host interface with support for up to 12 USB ports; six UHCI host controllers; two 
EHCI high-speed USB 2.0 host controllers 
ƒ
 
Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense 
ƒ
 
System Management Bus (SMBus) Specification, Version 2.0 with additional support for 
I
2
C devices 
ƒ
 
Low Pin Count (LPC) interface support 
ƒ
 
Firmware Hub (FWH) interface support 
ƒ
 
Serial Peripheral Interface (SPI) support