Integral INSSD128GP18MXZ ユーザーズマニュアル
5
25
-DIOR
26
Ground
27
IORDY
28
Ground
29
DMACK-
30
INTRQ
31
DA1
32
PDIAG-
33
DA0
34
DA2
35
CS0-
36
CS1-
37
DASP-
38
3.3V
39
3.3V
40
Reserved
2.2 Pin Description
Pin No.
Signal
I/O*
Description
03
-RESET
I
Hardware reset signal from the host
19, 17, 15, 13, 11,
09, 07, 05. 06, 08,
10, 12, 14, 16, 18,
20
DD0~DD15(Device Data)
I/O
16-bit bi-direction Data Bus. DD(7:0) are
used for 8-bit register transfers.
22
DMARQ(DMA Request)
O
For DMA data transfers. Device will
assert DMARQ when the device is ready
to transfer data to or from the host.
24
-DIOW(I/O Write)
I
This is the strobe signal used by the host
to write to the device register or Data
port
STOP(Stop UDMA Burst)
The host assert this signal during an
UDMA burst to stop the DMA burst
27
IORDY(I/O channel ready)
O
This signal is used to temporarily stop
the host register access (read or write)
when the device is not ready to respond
to a data transfer request.
DDMARDY(UDMA ready)
The device will assert this signal to
indicate that the device is ready to
receive UDMA data-out burst.
DSTROBE(UDMA data
strobe)
When UDMA mode DMA Read is active,
this signal is the data-in strobe generated
by the device.
29
-DMACK(DMA
acknowledge)
I
This signal is used by the host in respond
to DMARQ to initiate DMA transfer.