Intel Core i5-580M CP80617005487AD ユーザーズマニュアル
製品コード
CP80617005487AD
Signal Description
72
Datasheet
6.3
Reset and Miscellaneous Signals
Table 28.
Reset and Miscellaneous Signals (Sheet 1 of 2)
Signal Name
Description
Direction/Buffer
Type
BPM#[7:0]
Breakpoint and Performance Monitor
Signals: Outputs from the processor that
indicate the status of breakpoints and
programmable counters used for monitoring
processor performance.
Signals: Outputs from the processor that
indicate the status of breakpoints and
programmable counters used for monitoring
processor performance.
I/O
GTL
CFG[17:0]
Configuration Signals:
The CFG signals have a default value of '1' if
not terminated on the board.
CFG[2:0] - Reserved configuration pins. Test
points may be placed on these pins on a
common motherboard design.
CFG[3] – PCI Express* Static Lane
Numbering Reversal. Lane Reversal will be
applied across all 16 Lanes.
The CFG signals have a default value of '1' if
not terminated on the board.
CFG[2:0] - Reserved configuration pins. Test
points may be placed on these pins on a
common motherboard design.
CFG[3] – PCI Express* Static Lane
Numbering Reversal. Lane Reversal will be
applied across all 16 Lanes.
• 1: No lane reversal
• 0: Reversal
• 0: Reversal
CFG[4] - Embedded DisplayPort Detection:
This is used to detect the presence of a
device on the Embedded DisplayPort.
CFG[17:5] - Reserved configuration pins.
Note: Hardware straps are sampled on the
asserting edge of VCCPWRGOOD_0 and
VCCPWRGOOD_1 and latched inside the
processor.
This is used to detect the presence of a
device on the Embedded DisplayPort.
CFG[17:5] - Reserved configuration pins.
Note: Hardware straps are sampled on the
asserting edge of VCCPWRGOOD_0 and
VCCPWRGOOD_1 and latched inside the
processor.
I
CMOS
COMP0
Impedance compensation must be
terminated on the system board using a
precision resistor.
terminated on the system board using a
precision resistor.
I
A
COMP1
Impedance compensation must be
terminated on the system board using a
precision resistor.
terminated on the system board using a
precision resistor.
I
A
COMP2
Impedance compensation must be
terminated on the system board using a
precision resistor.
terminated on the system board using a
precision resistor.
I
A
COMP3
Impedance compensation must be
terminated on the system board using a
precision resistor.
terminated on the system board using a
precision resistor.
I
A
DBR#
Debug Reset: Used only in systems where
no debug port is implemented on the system
board. DBR# is used by a debug port
interposer so that an in-target probe can
drive system reset. This signal only routes
through the package and does not connect to
the processor silicon itself.
no debug port is implemented on the system
board. DBR# is used by a debug port
interposer so that an in-target probe can
drive system reset. This signal only routes
through the package and does not connect to
the processor silicon itself.
O